35
IDT72T6360 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE
x9, x18, x36 BIT WIDE CONFIGURATION
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 10, 2009
Figure 10. Empty Boundary - IDT Standard Mode
NO OPERATION
RCLK
REN
6357 drw24
EF
tCLK
tCLKH
tCLKL
tENH
tREF
tA
tOE
Q[35:0]
OE
WCLK
(1)
tSKEW1
WEN
D[35:0]
tENS
tENS
tENH
tDS
tDH
Word 0
1
2
t
OLZ
NO OPERATION
Last Word
Word 0
tENS
tENH
tDS tDH
tOHZ
Last Word
t
REF
tENH
tENS
tA
tA
tREF
tENS
tENH
Word 1
Word 1
NOTES:
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH after one RCLK cycle (plus tREFs). If tSKEW1 is
not met, then EF de-assertion may be delayed one extra RCLK cycle.
2. Settings: RCS = LOW, WCS = LOW, BM[3:0] = 1000, FWFT = LOW, ASYR = HIGH, and ASYW = HIGH.
6ns 7-5ns
Symbol Parameter Min. Max. Min. Max. Unit
tCLK Clock Cycle Time 6 — 7.5 — ns
tCLKH Clock High Time 2.7 — 3.5 — ns
tCLKL Clock Low Time 2.7 — 3.5 — ns
tDS Data Setup Time 2 — 2.5 — ns
tDH Data Hold Time 0.5 — 0.5 — ns
tENS Enable Setup Time 2 — 2.5 — ns
tENH Enable Hold Time 0.5 — 0.5 — ns
tA Data Access Time 1 4 1 5 ns
tREFs Read Clock to Synchronous EF/OR —4—5ns
t
SKEW1 Skew time between RCLK and WCLK for EF/OR and FF/IR in SDR 4 — 5 — ns
Figure 11. Empty Boundary - FWFT Mode
123
t
A
t
A
Last Word - 2
RCLK
REN
OR
WCLK
6357 drw25
WEN
D[35:0]
t
ENS
t
ENH
Q[35:0]
Word 0
t
DS
t
DH
Last Word - 3
t
A
Last Word - 1
t
REFs
t
SKEW1
Last Word
t
A
Word 0
t
REFs
NOTES:
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH after one RCLK cycle (plus tREFs).
If tSKEW1 is not met, then EF de-assertion may be delayed one extra RCLK cycle.
2. Settings: OE = LOW, RCS = LOW, WCS = LOW, BM[3:0] = 1000, FWFT = HIGH, ASYR = HIGH, and ASYW = HIGH.
