23
IDT72T6360 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE
x9, x18, x36 BIT WIDE CONFIGURATION
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 10, 2009
SIGNAL DESCRIPTIONS
INPUTS
DATA INPUTS (D0 - D35)
Data inputs for 36-bit wide data (D0 - D35), data inputs for 18-bit wide data
(D0 - D17) or data inputs for 9-bit wide data (D0 - D8).
CONTROLS
MASTER RESET (MRS)
A Master Reset is accomplished whenever the MRS input is toggled LOW
then HIGH. This operation sets the internal read and write pointers to the first
location of the RAM array. PAE will go LOW, PAF will go HIGH.
If FWFT is LOW during Master Reset then the IDT Standard mode, along
with EF and FF are selected. EF will go LOW and FF will go HIGH. If FWFT
is HIGH, then the First Word Fall Through mode (FWFT), along with IR and
OR, are selected. OR will go HIGH and IR will go LOW.
All configuration control signals must be set prior to the LOW to HIGH transition
of MRS.
During a Master Reset, the output register is initialized to all zeroes. A Master
Reset is required after power up, before a write operation can take place. MRS
is an asynchronous function.
See Figure 6, Master Reset and Initialization, for the relevant timing diagram.
PARTIAL RESET (PRS)
A Partial Reset is accomplished whenever the PRS input is toggled LOW then
HIGH. As in the case of the Master Reset, the internal read and write pointers
are set to the first location of the RAM array, PAE goes LOW, and PAF goes
HIGH.
Whichever mode is active at the time of Partial Reset, IDT Standard mode or
First Word Fall Through, that mode will remain selected. If the IDT Standard
mode is active, then FF will go HIGH and EF will go LOW. If the First Word Fall
Through mode is active, then OR will go HIGH, and IR will go LOW.
Following Partial Reset, all values held in the offset registers remain
unchanged. The output register is initialized to all zeroes. PRS is asynchronous.
A Partial Reset is useful for resetting the device during the course of operation,
when reprogramming programmable flag offset settings may not be convenient.
See Figure 7, Partial Reset, for the relevant timing diagram.
ASYNCHRONOUS WRITE (ASYW)
The write port can be configured for either synchronous or asynchronous
mode of operation. If during Master Reset the ASYW input is LOW, then
asynchronous operation of the write port will be selected. During asynchronous
operation of the write port the WCLK input becomes WR input, this is the
asynchronous write strobe input. A rising edge on WR will write data present
on the data inputs into the sequential flow-control device (SFC). (WEN must be
LOW when using the write port in asynchronous mode).
When the write port is configured for asynchronous operation the device must
be operating on IDT standard mode, FWFT mode is not permissable. The full
flag (FF) and programmable almost full flag (PAF) operates in an asynchronous
manner, that is, the full flag and PAF flag will be updated based in both a write
operation and read operation. Note, if asynchronous mode is selected, FWFT
is not permissible. Refer to Figure 24, Asynchronous Write and PAE flag – IDT
Standard mode and Figure 25, Asynchronous Write and PAF flag – IDT
Standard mode for relevant timing and operational waveforms.
ASYNCHRONOUS READ (ASYR)
The read port can be configured for either synchronous or asynchronous
mode of operation. If during a Master Reset the ASYR input is LOW, then
asynchronous operation of the read port will be selected. During asynchronous
operation of the read port the RCLK input becomes RD input, this is the
asynchronous read strobe input. A rising edge on RD will read data from the
SFC via the output register and data output port. (REN must be tied LOW during
asynchronous operation of the read port).
The OE input provides three-state control of the Qn output bus, in an
asynchronous manner.
When the read port is configured for asynchronous operation the device must
be operating on IDT standard mode, FWFT mode is not permissible if the read
port is asynchronous. The Empty Flag (EF) and programmable almost empty
flag (PAF) operates in an asynchronous manner, that is, the empty flag and PAE
will be updated based on both a read operation and a write operation. Refer
to Figure 23, Asynchronous Read and PAF flag – IDT Standard mode, Figure
26, Asynchronous Empty Boundary – IDT Standard mode, Figure 27,
Asynchronous Full Boundary – IDT Standard mode,, and Figure 28, Asyn-
chronous Read and PAE flag – IDT Standard mode, for relevant timing and
operational waveforms.
FIRST WORD FALL THROUGH (FWFT)
During Master Reset, the state of the FWFT input determines whether the
device will operate in IDT standard mode or First Word Fall Through (FWFT)
mode.
If, at the time of Master Reset, FWFT is LOW, then IDT Standard mode will
be selected. This mode uses the Empty Flag (EF) to indicate whether or not
there are any words present in the SFC. It also uses the Full Flag function (FF)
to indicate whether or not the SFC has any free space for writing. In IDT
Standard mode, every word read from the SFC, including the first, must be
requested using the Read Enable (REN) and RCLK.
If, at the time of Master Reset, FWFT is HIGH, then FWFT mode will be
selected. This mode uses Output Ready (OR) to indicate whether or not there
is valid data at the data outputs (Qn). It also uses Input Ready (IR) to indicate
whether or not the SFC has any free space for writing. In the FWFT mode, the
first word written to an empty SFC goes directly to Qn after three RCLK rising
edges, REN = LOW is not necessary. Subsequent words must be accessed
using the Read Enable (REN) and RCLK.
WRITE STROBE AND WRITE CLOCK (WR/WCLK)
If synchronous operation of the write port has been selected via ASYW, this
input behaves as WCLK.
A write cycle is initiated on the rising edge of the WCLK input. Data setup and
hold times must be met with respect to the LOW-to-HIGH transition of the WCLK.
It is permissible to stop the WCLK. Note that while WCLK is idle, the FF/IR, and
PAF flags will not be updated. The Write and Read Clocks can either be
independent or coincident.
If asynchronous operation has been selected this input is WR (write strobe).
Data is asynchronously written into the SFC via the Dn inputs whenever there
is a rising edge on WR. In this mode the WEN input must be LOW.
WRITE ENABLE (WEN)
When the WEN input is LOW, data may be loaded into the SFC on the rising
edge of every WCLK cycle if the device is not full. Data is stored in the RAM
array sequentially and independently of any ongoing read operation.
When WEN is HIGH, no new data is written in the SFC.
To prevent data overflow in the IDT Standard mode, FF will go LOW, inhibiting
further write operations. Upon the completion of a valid read cycle, FF will go
HIGH allowing a write to occur. The FF is updated by two WCLK cycles + tSKEW
after the RCLK cycle.
