30
IDT72T6360 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE
x9, x18, x36 BIT WIDE CONFIGURATION
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 10, 2009
AC ELECTRICAL CHARACTERISTICS
(1)
⎯ SYNCHRONOUS TIMING
(Commercial: VCC = 2.5V ± 5%, TA = 0°C to +70°C;Industrial: VCC = 2.5V ± 5%, TA = -40°C to +85°C)
NOTES:
1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode.
2. Industrial temperature range product for the 7.5ns speed grade is available as a standard device. All other speed grades are available by special order.
Commercial Com'l & Ind'l
(2)
IDT72T6360L6 IDT72T6360L7-5
Symbol Parameter Min. Max. Min. Max. Unit
fS Synchronous Clock Cycle Frequency — 166 — 133 MHz
tA Data Access Time 1 4 1 5 ns
tCLK Clock Cycle Time 6 — 7.5 — ns
tCLKH Clock High Time 2.7 — 3.5 — ns
tCLKL Clock Low Time 2.7 — 3.5 — ns
tDS Data Setup Time 2 — 2.5 — ns
tDH Data Hold Time 0.5 — 0.5 — ns
tENS Enable Setup Time 2 — 2.5 — ns
tENH Enable Hold Time 0.5 — 0.5 — ns
tRS Reset Pulse Width 10 — 10 — ns
tRSU Reset Setup Time 15 — 15 — ns
tRSH Reset Hold Time 10 — 10 — ns
tPL Reset to PLL Lock 20 — 20 — µs
tRSF Reset to Flag and Output — 15 — 15 ns
tOHZ Output enable to High-Z 1 4 1 5 ns
tOE Output Enable Valid 1 4 1 5 ns
fMC Master Clock Cycle Frequency 32 34 32 34 MHz
tMCYC Master Clock Cycle Time 29.4 31.3 29.4 31.3 ns
tMCKH Master Clock Cycle HIGH 0.45 0.55 0.45 0.55 tMCYC
tMCKL Master Clock Cycle LOW 0.45 0.55 0.45 0.55 tMCYC
fSC Serial Clock Cycle Frequency — 10 — 10 MHz
tSCLK Serial Clock Cycle 100 — 100 — ns
tSCLKH Serial Clock HIGH 45 — 45 — ns
tSCLKL Serial Clock LOW 45 — 45 — ns
tSDS Serial Data Setup 15 — 15 — ns
tSDH Serial Data Hold 5 — 5 — ns
tSENS Serial Enable Setup 5 — 5 — ns
tSENH Serial Enable Hold 5 — 5 — ns
tASO Serial Output Data Access Time — 20 — 20 ns
tWFFs Write Clock to Synchronous FF/IR —4—5ns
tREFs Read Clock to Synchronous EF/OR —4—5ns
tPAFs WCLK to Synchronous PAF —4—5ns
tPAEs RCLK to Synchronous PAE —4—5ns
tSKEW1 Skew time between RCLK and WCLK for EF/OR and FF/IR in SDR 4 — 5 — ns
tSKEW2 Skew time between RCLK and WCLK for PAE/PAF 5—7—ns
tWCSS WCS Setup Time 2 — 2.5 — ns
tWCSH WCS Hold Time 0.5 — 0.5 — ns
fC1 Memory Clock Cycle Frequency at 166MHz 160 170 — — MHz
fC2 Memory Clock Cycle Frequency at 133MHz 128 136 128 136 MHz
tCK1 Memory Clock Cycle Time at 166MHz 6.2 5.9 — — ns
tCK2 Memory Clock Cycle Time at 133MHz 7.8 7.3 7.8 7.3 ns
tCKH1 Memory Clock Cycle HIGH at 166MHz 0.45 0.55 — — tCK1
tCKH2 Memory Clock Cycle HIGH at 133MHz 0.45 0.55 0.45 0.55 tCK2
tCKL1 Memory Clock Cycle LOW at 166MHz 0.45 0.55 — — tCK1
tCKL2 Memory Clock Cycle LOW at 133MHz 0.45 0.55 0.45 0.55 tCK2
