TDA9983BHW/15/C1:5 Datasheet TDA9983BHW/8/C1,55, TDA9983BHW/15/C1:5, TDA9983BHW/8/C1,51 | P10-P12

Product data sheet Rev. 01 — 20 May 2008 10 of 119

NXP Semiconductors

TDA9983B

150 MHz pixel rate HDMI transmitter

Table 6. RGB 4 :4:4 mappings

RGB 4:4:4 (3

×

8-bit) external synchronization single edge.

Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 45h; VIP_CNTRL_2 = 01h.

Video port A Video port B Video port C Control

Pin RGB 4 : 4 : 4 Pin RGB 4 : 4 : 4 Pin RGB 4 : 4 : 4 Pin RGB 4 :4:4

VPA[0] B[0] VPB[0] G[0] VPC[0] R[0] HSYNC/HREF used

VPA[1] B[1] VPB[1] G[1] VPC[1] R[1] VSYNC/VREF used

VPA[2] B[2] VPB[2] G[2] VPC[2] R[2] DE/FREF used

VPA[3] B[3] VPB[3] G[3] VPC[3] R[3]

VPA[4] B[4] VPB[4] G[4] VPC[4] R[4]

VPA[5] B[5] VPB[5] G[5] VPC[5] R[5]

VPA[6] B[6] VPB[6] G[6] VPC[6] R[6]

VPA[7] B[7] VPB[7] G[7] VPC[7] R[7]

DE could also be generated from HSYNC/HREF and VSYNC/VREF

Fig 3. Pixel encoding in RGB 4:4:4 (rising edge) input

001aag380

Bxxx Bxxx...B3B2B1B0

HSYNC/HREF

VSYNC/VREF

DE/FREF

Gxxx Gxxx...G3G2G1G0

Rxxx Rxxx...R3R2R1R0

CONTROL

INPUTS

VPA[7:0]

VCLK

VPB[7:0]

VPC[7:0]

Product data sheet Rev. 01 — 20 May 2008 11 of 119

NXP Semiconductors

TDA9983B

150 MHz pixel rate HDMI transmitter

Table 7. YC

B

C

R

4:4:4 mappings

YC

B

C

R

4:4:4 (3

×

8-bit) external synchronization single edge.

Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 45h; VIP_CNTRL_2 = 01h.

Video port A Video port B Video port C Control

Pin YC

B

C

R

4:4:4 Pin YC

B

C

R

4:4:4 Pin YC

B

C

R

4:4:4 Pin YC

B

C

R

4:4:4

VPA[0] C

B

[0] VPB[0] Y[0] VPC[0] C

R

[0] HSYNC/HREF used

VPA[1] C

B

[1] VPB[1] Y[1] VPC[1] C

R

[1] VSYNC/VREF used

VPA[2] C

B

[2] VPB[2] Y[2] VPC[2] C

R

[2] DE/FREF used

VPA[3] C

B

[3] VPB[3] Y[3] VPC[3] C

R

[3]

VPA[4] C

B

[4] VPB[4] Y[4] VPC[4] C

R

[4]

VPA[5] C

B

[5] VPB[5] Y[5] VPC[5] C

R

[5]

VPA[6] C

B

[6] VPB[6] Y[6] VPC[6] C

R

[6]

VPA[7] C

B

[7] VPB[7] Y[7] VPC[7] C

R

[7]

DE could also be generated from HSYNC/HREF and VSYNC/VREF

Fig 4. Pixel encoding in YC

B

C

R

4 : 4 : 4 (rising edge) input

001aag381

C

B

xxx C

B

xxx...C

B

3C

B

2C

B

1C

B

0

HSYNC/HREF

VSYNC/VREF

DE/FREF

Yxxx Yxxx...Y3Y2Y1Y0

C

R

xxx C

R

xxx...C

R

3C

R

2C

R

1C

R

0

CONTROL

INPUTS

VPA[7:0]

VCLK

VPB[7:0]

VPC[7:0]

Product data sheet Rev. 01 — 20 May 2008 12 of 119

NXP Semiconductors

TDA9983B

150 MHz pixel rate HDMI transmitter

Table 8. YC

B

C

R

4:2:2 ITU656-like external synchronization single edge mappings

YC

B

C

R

4:2:2 ITU656-like external synchronization single edge.

Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 00h.

Video port A Video port B Control

Pin YC

B

C

R

4 : 2 : 2 (ITU656-like) Pin YC

B

C

R

4 : 2 : 2 (ITU656-like) Pin YC

B

C

R

4:2:2

VPA[0] C

B

[0] Y

0

[0] C

R

[0] Y

1

[0] VPB[0] C

B

[4] Y

0

[4] C

R

[4] Y

1

[4] HSYNC/HREF used

VPA[1] C

B

[1] Y

0

[1] C

R

[1] Y

1

[1] VPB[1] C

B

[5] Y

0

[5] C

R

[5] Y

1

[5] VSYNC/VREF used

VPA[2] C

B

[2] Y

0

[2] C

R

[2] Y

1

[2] VPB[2] C

B

[6] Y

0

[6] C

R

[6] Y

1

[6] DE/FREF used

VPA[3] C

B

[3] Y

0

[3] C

R

[3] Y

1

[3] VPB[3] C

B

[7] Y

0

[7] C

R

[7] Y

1

[7]

VPA[4] - - - - VPB[4] C

B

[8] Y

0

[8] C

R

[8] Y

1

[8]

VPA[5] - - - - VPB[5] C

B

[9] Y

0

[9] C

R

[9] Y

1

[9]

VPA[6] - - - - VPB[6] C

B

[10] Y

0

[10] C

R

[10] Y

1

[10]

VPA[7] - - - - VPB[7] C

B

[11] Y

0

[11] C

R

[11] Y

1

[11]

Fig 5. Pixel encoding YC

B

C

R

4 : 2 : 2 ITU656-like external synchronization single edge (rising edge) input

001aag383

C

R

xxx Yxxx...Y1C

R

0Y0C

B

0

HSYNC/HREF

VSYNC/VREF

DE/FREF

CONTROL

INPUTS

VPB[7:0]; VPA[3:0]

VCLK

TDA9983BHW/15/C1:5

TDA9983BHW/15/C1:5

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