TDA9983B_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 20 May 2008 62 of 119
NXP Semiconductors
TDA9983B
150 MHz pixel rate HDMI transmitter
Table 79. AUDIO_DIV register (address 0Eh) bit description
Legend: * = default value
Bit Symbol Access Value Description
7 to 3 x R/W 0000 0* undefined
2 to 0 AUDIO_DIV[2:0] R/W audio divider: not guaranteed; under
reservation (ip_manual)
000 Audio_Clk_Out = SERclk / 1
001 Audio_Clk_Out = SERclk / 2
010 Audio_Clk_Out = SERclk / 4
011* Audio_Clk_Out = SERclk / 8
100 Audio_Clk_Out = SERclk / 16
101 Audio_Clk_Out = SERclk / 32
11X do not use
Table 80. TESTx registers (address 0Fh and 10h) bit description
Legend: * = default value
Address Register Bit Symbol Access Value Description
0Fh TEST1 7 to 5 x R/W 000* undefined
4 TSTSERPHOE R/W test serializer phoe
0* srl_tst_ph2_o = '0'; srl_tst_ph3_o = '0'
1 srl_tst_ph2_o = 'active'; srl_tst_ph3_o = 'active'
3 to 2 x R/W 00* undefined
1 TST_NOSC R/W test N oscillator: test mode nosc predividers
0* normal mode; input nosc predivider = PLL
oscillator output
1 test mode; input nosc predivider = PLL
reference input
0 TST_HVP R/W test high voltage protection: test high voltage
protection cells
0* normal PLL mode
1 test mode; HVP input forced to V
DDA(PLL_3V3)
10h TEST2 7 to 2 x R/W 0000 00* undefined
1 PWD1V8 R/W power-down 1.8 V
0* normal operation
1 sleep mode PLLs
0 DIVTESTOE R/W divider tests output enable: enable activity of
scaler PLL dividers test outputs
0* test outputs = '0'
1 test outputs = active
