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TDA9983B_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 20 May 2008 4 of 119
NXP Semiconductors
TDA9983B
150 MHz pixel rate HDMI transmitter
6. Block diagram
(1) Block can be bypassed.
Fig 1. Block diagram
001aag248
VPA[7:0]
VIDEO
INPUT
PROCESSOR
UPSCALER
(1)
VIDEO PROCESSING
3 × 8-bit
RGB
YC
B
C
R
4 : 4 : 4
2 × 12-bit
or 1 × 12-bit
YC
B
C
R
4 : 2 : 2
ITU656 or ITU656-like
UPSAMPLING
FROM
4 : 2 : 2
TO
4 : 4 : 4
(1)
DOWNSAMPLING
FROM
4 : 4 : 4
TO
4 : 2 : 2
(1)
COLOR
SPACE
CONVERTER
RGB TO YUV
YUV TO RGB
(4 : 4 : 4)
(1)
DEINTERLACER
INTRAFIELD
(1)
TDA9983B
AUDIO
PROCESSING
HPD
MANAGEMENT
DATA
ISLAND
PACKET
INFORMATION
FRAMES AND
PACKETS
VPB[7:0]
VPC[7:0]
VSYNC/VREF
HSYNC/HREF
DE/FREF
VCLK
2
1
80
68 to 70,
75 to 79
57 and 58,
61 to 65,
67
49 to 56
66
HPD
HDMI
SERIALIZER
26
TXC
27
TXC+
29
TX0
30
TX0+
32
TX1
33
TX1+
35
TX2
36
TX2+
DDC_SCL
DDC_SDA
20
19
INT
17
I
2
C-BUS
SLAVE
DDC-BUS
IRQ
GENERATION
I2C_SCL I2C_SDA A0 A1
43 44 41 40
AP7 to AP0
4 to 11
ACLK
12
18
V
SSD
14, 47,
72
V
SSC
15, 60,
73
V
SSA(FRO_3V3)
22
V
SSA(PLL_3V3)
39
TM
21
EXT_SWING
24
V
SSH
25, 31,
37
V
SSA(PLL_1V8)
46
HARD
RESET
RST_N
42
V
PP
V
DDD(3V3)
V
DDC(1V8)
V
DDA(
FRO_3V3)
V
DDH(3V3)
V
DDA(PLL_3V3)
3
13, 48,
71
16, 45,
59, 74
23
28, 34
38
TDA9983B_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 20 May 2008 5 of 119
NXP Semiconductors
TDA9983B
150 MHz pixel rate HDMI transmitter
7. Pinning information
7.1 Pinning
7.2 Pin description
Fig 2. Pin configuration
TDA9983B
HSYNC/HREF V
SSC
VSYNC/VREF V
DDC(1V8)
V
PP
VPB[6]
AP7 VPB[7]
AP6 VPC[0]
AP5 VPC[1]
AP4 VPC[2]
AP3 VPC[3]
AP2 VPC[4]
AP1 VPC[5]
AP0 VPC[6]
ACLK VPC[7]
V
DDD(3V3)
V
DDD(3V3)
V
SSD
V
SSD
V
SSC
V
SSA(PLL_1V8)
V
DDC(1V8)
V
DDC(1V8)
INT I2C_SDA
HPD I2C_SCL
DDC_SDA RST_N
DDC_SCL A0
TM DE/FREF
V
SSA(FRO_3V3)
VPA[0]
V
DDA(FRO_3V3)
VPA[1]
EXT_SWING VPA[2]
V
SSH
VPA[3]
TXC VPA[4]
TXC+ V
DDC(1V8)
V
DDH(3V3)
V
SSC
TX0 V
SSD
TX0+ V
DDD(3V3)
V
SSH
VPA[5]
TX1 VPA[6]
TX1+ VPA[7]
V
DDH(3V3)
VPB[0]
TX2 VCLK
TX2+ VPB[1]
V
SSH
VPB[2]
V
DDA(PLL_3V3)
VPB[3]
V
SSA(PLL_3V3)
VPB[4]
A1 VPB[5]
001aag249
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
Table 4. Pin description
Symbol Pin Type
[1]
Description
HSYNC/HREF 1 I horizontal synchronization or reference input
VSYNC/VREF 2 I vertical synchronization or reference input
V
PP
3 P programming voltage (must be connected to the ground of
the digital core in normal operation)
AP7 4 I audio port 7 input; auxiliary (AUX)
AP6 5 I audio port 6 input; S/PDIF stream
AP5 6 I audio port 5 input; optional master clock MCLK for S/PDIF
TDA9983B_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 20 May 2008 6 of 119
NXP Semiconductors
TDA9983B
150 MHz pixel rate HDMI transmitter
AP4 7 I audio port 4 input; I
2
S-bus 3
AP3 8 I audio port 3 input; I
2
S-bus 2
AP2 9 I audio port 2 input; I
2
S-bus 1
AP1 10 I audio port 1 input; I
2
S-bus 0
AP0 11 I audio port 0 input; word select WS for I
2
S-bus
ACLK 12 I audio clock input; clock SCK for I
2
S-bus
V
DDD(3V3)
13 P supply voltage for input ports (3.3 V)
V
SSD
14 G ground for input ports
V
SSC
15 G ground for digital core
V
DDC(1V8)
16 P supply voltage for digital core (1.8 V)
INT 17 O interrupt output (open drain); warns the external
microprocessor that a special event has occurred; must be
connected to a pull-up resistor; 5 V tolerant
HPD 18 I hot plug detect input; 5 V tolerant
DDC_SDA 19 I/O DDC-bus data input/output (open drain); must be connected
to a pull-up resistor; 5 V tolerant
DDC_SCL 20 O DDC-bus clock output (open drain); must be connected to a
pull-up resistor; 5 V tolerant
TM 21 I internal test mode input (must be connected to the ground of
the digital core in normal operation)
V
SSA(FRO_3V3)
22 G analog ground for free running oscillator
V
DDA(FRO_3V3)
23 P analog supply voltage for free running oscillator (3.3 V)
EXT_SWING 24 I external swing adjust input; a fixed resistor must be
connected between this pin and V
DDH(3V3)
to set the HDMI
output swing (see
Section 8.14.1)
V
SSH
25 G ground for HDMI transmitter
TXC 26 O negative clock channel for HDMI output
TXC+ 27 O positive clock channel for HDMI output
V
DDH(3V3)
28 P supply voltage for HDMI transmitter (3.3 V)
TX0 29 O negative data channel 0 for HDMI output
TX0+ 30 O positive data channel 0 for HDMI output
V
SSH
31 G ground for HDMI transmitter
TX1 32 O negative data channel 1 for HDMI output
TX1+ 33 O positive data channel 1 for HDMI output
V
DDH(3V3)
34 P supply voltage for HDMI transmitter (3.3 V)
TX2 35 O negative data channel 2 for HDMI output
TX2+ 36 O positive data channel 2 for HDMI output
V
SSH
37 G ground for HDMI transmitter
V
DDA(PLL_3V3)
38 P analog supply voltage for PLL (3.3 V)
V
SSA(PLL_3V3)
39 G analog ground reference for PLL
A1 40 I I
2
C-bus slave address input 1; bit 1
A0 41 I I
2
C-bus slave address input 0; bit 0
RST_N 42 I hard reset input; active LOW
Table 4. Pin description
…continued
Symbol Pin Type
[1]
Description

TDA9983BHW/15/C1:5

Mfr. #:
Manufacturer:
Description:
IC HDMI TX 150MHZ 80-HTQFP
Lifecycle:
New from this manufacturer.
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