TDA9983BHW/15/C1:5 Datasheet TDA9983BHW/8/C1,55, TDA9983BHW/15/C1:5, TDA9983BHW/8/C1,51 | P58-P60

Product data sheet Rev. 01 — 20 May 2008 58 of 119

NXP Semiconductors

TDA9983B

150 MHz pixel rate HDMI transmitter

Table 68. PLL_SERIAL_2 register (address 01h) bit description

Legend: * = default value

Bit Symbol Access Value Description

7 to 4 SRL_PR[3:0] R/W serializer pixel repetition: pixel repetition

factor (ip_auto)

0000* pr = 1 (ip_auto = 400 nA)

0001 pr = 2 (ip_auto = 200 nA)

0010 pr = 3 (ip_auto = 133 nA)

0011 pr = 4 (ip_auto = 100 nA)

0100 pr = 5 (ip_auto = 80 nA)

0101 pr = 6 (ip_auto = 66 nA)

0110 pr = 7 (ip_auto = 57 nA)

0111 pr = 8 (ip_auto = 50 nA)

1000 pr = 9 (ip_auto = 50 nA)

1001 pr = 10 (ip_auto = 50 nA)

other undeﬁned

3 to 2 x R/W 00* undeﬁned

1 to 0 SRL_NOSC[1:0] R/W serializer N oscillator: predivider division

factor

00* div_by_1; PLL output frequency range =

(800 to 1500) Msample/s (Iz = 1.0+)

01 div_by_2; PLL output frequency range =

(400 to 800) Msample/s (Iz = 1.5+)

10 div_by_4; PLL output frequency range =

(200 to 400) Msample/s (Iz = 2.0+)

11 div_by_4; PLL output frequency range =

(200 to 400) Msample/s (Iz = 2.0+)

Table 69. PLL_SERIAL_3 register (address 02h) bit description

Legend: * = default value

Bit Symbol Access Value Description

7 to 5 x R/W 000* undeﬁned

4 SRL_PXIN_SEL R/W serializer pixel input select

0* PXINclko = SCAclko

1 PXINclko = SCAclko / 2

3 to 2 x R/W 00* undeﬁned

1 SRL_DE R/W serializer double edge: double edge divider

in feedback loop

0* no division

1 divide by 2

0 SRL_CCIR R/W serializer CCIR

0* pllsrl_in = pllsrl_reﬁn

1 pllsrl_in = pllsrl_reﬁn / 2

Product data sheet Rev. 01 — 20 May 2008 59 of 119

NXP Semiconductors

TDA9983B

150 MHz pixel rate HDMI transmitter

Table 70. SERIALIZER register (address 03h) bit description

Legend: * = default value

Bit Symbol Access Value Description

7 to 4 SRL_PHASE3[3:0] R/W 0000* serializer phase 3: phase selection of third

storage level of the serializer input

3 to 0 SRL_PHASE2[3:0] R/W 0000* serializer phase 2: phase selection of second

storage level of the serializer input

Table 71. BUFFER_OUT register (address 04h) bit description

Legend: * = default value

Bit Symbol Access Value Description

7 to 4 x R/W 0000* undeﬁned

3 to 2 SRL_FORCE[1:0] R/W serializer force

00* TMDS outputs active (normal operation)

01 TMDS outputs active (normal operation)

10 TMDS outputs forced '0'

11 TMDS outputs forced '1'

1 to 0 SRL_CLK[1:0] R/W serializer clock

00* TMDS TXC = TMDSclk (normal operation)

01 TMDS TXC = SERclk / 2

10 TMDS TXC = undeﬁned

11 TMDS TXC = SERclk

Table 72. PLL_SCG1 register (address 05h) bit description

Legend: * = default value

Bit Symbol Access Value Description

7 to 1 x R/W 0000

000*

undeﬁned

0 SCG_FDN R/W scg fnd

0 normal (PLL loop active)

1* standby (PLL loop open)

Table 73. PLL_SCG2 register (address 06h) bit description

Legend: * = default value

Bit Symbol Access Value Description

7 BYPASS_SCG R/W bypass scg

0 SCAclko = scg_nosc predivider output

1* SCAclko = pllscg_inref

6 to 5 x R/W 00* undeﬁned

4 SELPLLCLKIN R/W select PLL clock input

0 pllscg_in = pllsca_inref

1* pllscg_in = pllclkin

3 to 2 x R/W 00* undeﬁned

Product data sheet Rev. 01 — 20 May 2008 60 of 119

NXP Semiconductors

TDA9983B

150 MHz pixel rate HDMI transmitter

1 to 0 SCG_NOSC[1:0] R/W scg N oscillator

00* div_by_1; PLL output frequency range =

(80 to 150) Msample/s

01 div_by_2; PLL output frequency range =

(40 to 80) Msample/s

10 div_by_4; PLL output frequency range =

(20 to 40) Msample/s

11 div_by_8; PLL output frequency range =

(10 to 20) Msample/s

Table 73. PLL_SCG2 register (address 06h) bit description

…continued

Legend: * = default value

Bit Symbol Access Value Description

Table 74. PLL_SCGNx registers (address 07h to 08h) bit description

Legend: * = default value

Address Register Bit Symbol Access Value Description

08h PLL_SCGN2 7 to 3 x R/W 0000 0* undeﬁned

2 to 0 SCG_NDIV[10:8] R/W 000* scg N divider: PLL feedback oscillator

divider

07h PLL_SCGN1 7 to 0 SCG_NDIV[7:0] R/W FAh*

Table 75. PLL_SCGRx registers (address 09h to 0Ah) bit description

Legend: * = default value

Address Register Bit Symbol Access Value Description

0Ah PLL_SCGR2 7 to 1 x R/W 0000 000* undeﬁned

0 SCG_RDIV[8] R/W 0* scg R divider: divider value of the PLL

reference input clock

09h PLL_SCGR1 7 to 0 SCG_RDIV[7:0] R/W 5Bh*

Table 76. PLL_DE register (address 0Bh) bit description

Legend: * = default value

Bit Symbol Access Value Description

7 BYPASS_PLLDE R/W bypass PLL double edge

0 pllde0 = de_nosc predivider output

1* pllde0 = pllde_inref

6 x R/W 0* undeﬁned

5 to 4 PLLDE_NOSC[1:0] R/W PLL double edge N oscillator

00* div_by_1; PLL output frequency range =

(80 to 150) Msample/s

01 div_by_2; PLL output frequency range =

(40 to 80) Msample/s

10 div_by_4; PLL output frequency range =

(20 to 40) Msample/s

11 div_by_8; PLL output frequency range =

(10 to 20) Msample/s

3 x R/W 0* undeﬁned

TDA9983BHW/15/C1:5

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