TDA9983BHW/15/C1:5 Datasheet TDA9983BHW/8/C1,55, TDA9983BHW/15/C1:5, TDA9983BHW/8/C1,51 | P13-P15

Product data sheet Rev. 01 — 20 May 2008 13 of 119

NXP Semiconductors

TDA9983B

150 MHz pixel rate HDMI transmitter

Table 9. YC

B

C

R

4:2:2 ITU656-like external synchronization double edge mappings

YC

B

C

R

4:2:2 ITU656-like external synchronization double edge.

Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 00h.

Video port A Video port B Control

Pin YC

B

C

R

4 : 2 : 2 (ITU656-like) Pin YC

B

C

R

4 : 2 : 2 (ITU656-like) Pin YC

B

C

R

4:2:2

VPA[0] C

B

[0] Y

0

[0] C

R

[0] Y

1

[0] VPB[0] C

B

[4] Y

0

[4] C

R

[4] Y

1

[4] HSYNC/HREF used

VPA[1] C

B

[1] Y

0

[1] C

R

[1] Y

1

[1] VPB[1] C

B

[5] Y

0

[5] C

R

[5] Y

1

[5] VSYNC/VREF used

VPA[2] C

B

[2] Y

0

[2] C

R

[2] Y

1

[2] VPB[2] C

B

[6] Y

0

[6] C

R

[6] Y

1

[6] DE/FREF used

VPA[3] C

B

[3] Y

0

[3] C

R

[3] Y

1

[3] VPB[3] C

B

[7] Y

0

[7] C

R

[7] Y

1

[7]

VPA[4] - - - - VPB[4] C

B

[8] Y

0

[8] C

R

[8] Y

1

[8]

VPA[5] - - - - VPB[5] C

B

[9] Y

0

[9] C

R

[9] Y

1

[9]

VPA[6] - - - - VPB[6] C

B

[10] Y

0

[10] C

R

[10] Y

1

[10]

VPA[7] - - - - VPB[7] C

B

[11] Y

0

[11] C

R

[11] Y

1

[11]

Fig 6. Pixel encoding YC

B

C

R

4 : 2 : 2 ITU656-like external synchronization double edge (rising and falling) input

001aag382

C

R

xxx Yxxx...Y1C

R

0Y0C

B

0

HSYNC/HREF

VSYNC/VREF

DE/FREF

VPB[7:0]; VPA[3:0]

VCLK

CONTROL

INPUTS

Product data sheet Rev. 01 — 20 May 2008 14 of 119

NXP Semiconductors

TDA9983B

150 MHz pixel rate HDMI transmitter

Table 10. YC

B

C

R

4:2:2 ITU656-like embedded synchronization single edge mappings

YC

B

C

R

4:2:2 ITU656-like embedded synchronization single edge.

Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 00h.

Video port A Video port B Control

Pin YC

B

C

R

4 : 2 : 2 (ITU656-like) Pin YC

B

C

R

4 : 2 : 2 (ITU656-like) Pin YC

B

C

R

4:2:2

VPA[0] C

B

[0] Y

0

[0] C

R

[0] Y

1

[0] VPB[0] C

B

[4] Y

0

[4] C

R

[4] Y

1

[4] HSYNC/HREF not used

VPA[1] C

B

[1] Y

0

[1] C

R

[1] Y

1

[1] VPB[1] C

B

[5] Y

0

[5] C

R

[5] Y

1

[5] VSYNC/VREF not used

VPA[2] C

B

[2] Y

0

[2] C

R

[2] Y

1

[2] VPB[2] C

B

[6] Y

0

[6] C

R

[6] Y

1

[6] DE/FREF not used

VPA[3] C

B

[3] Y

0

[3] C

R

[3] Y

1

[3] VPB[3] C

B

[7] Y

0

[7] C

R

[7] Y

1

[7]

VPA[4] - - - - VPB[4] C

B

[8] Y

0

[8] C

R

[8] Y

1

[8]

VPA[5] - - - - VPB[5] C

B

[9] Y

0

[9] C

R

[9] Y

1

[9]

VPA[6] - - - - VPB[6] C

B

[10] Y

0

[10] C

R

[10] Y

1

[10]

VPA[7] - - - - VPB[7] C

B

[11] Y

0

[11] C

R

[11] Y

1

[11]

Fig 7. Pixel encoding YC

B

C

R

4 : 2 : 2 ITU656-like embedded synchronization single edge (rising edge) input

001aag385

C

R

xxx Yxxx...Y1C

R

0Y0C

B

0VPB[7:0]; VPA[3:0]

VCLK

Product data sheet Rev. 01 — 20 May 2008 15 of 119

NXP Semiconductors

TDA9983B

150 MHz pixel rate HDMI transmitter

Table 11. YC

B

C

R

4:2:2 ITU656-like embedded synchronization double edge mappings

YC

B

C

R

4:2:2 ITU656-like embedded synchronization double edge.

Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 00h.

Video port A Video port B Control

Pin YC

B

C

R

4 : 2 : 2 (ITU656-like) Pin YC

B

C

R

4 : 2 : 2 (ITU656-like) Pin YC

B

C

R

4:2:2

VPA[0] C

B

[0] Y

0

[0] C

R

[0] Y

1

[0] VPB[0] C

B

[4] Y

0

[4] C

R

[4] Y

1

[4] HSYNC/HREF not used

VPA[1] C

B

[1] Y

0

[1] C

R

[1] Y

1

[1] VPB[1] C

B

[5] Y

0

[5] C

R

[5] Y

1

[5] VSYNC/VREF not used

VPA[2] C

B

[2] Y

0

[2] C

R

[2] Y

1

[2] VPB[2] C

B

[6] Y

0

[6] C

R

[6] Y

1

[6] DE/FREF not used

VPA[3] C

B

[3] Y

0

[3] C

R

[3] Y

1

[3] VPB[3] C

B

[7] Y

0

[7] C

R

[7] Y

1

[7]

VPA[4] - - - - VPB[4] C

B

[8] Y

0

[8] C

R

[8] Y

1

[8]

VPA[5] - - - - VPB[5] C

B

[9] Y

0

[9] C

R

[9] Y

1

[9]

VPA[6] - - - - VPB[6] C

B

[10] Y

0

[10] C

R

[10] Y

1

[10]

VPA[7] - - - - VPB[7] C

B

[11] Y

0

[11] C

R

[11] Y

1

[11]

Fig 8. Pixel encoding YC

B

C

R

4 : 2 : 2 ITU656-like embedded synchronization double edge (rising and falling)

input

001aag384

C

R

xxx Yxxx...Y1C

R

0Y0C

B

0VPB[7:0]; VPA[3:0]

VCLK

TDA9983BHW/15/C1:5

TDA9983BHW/15/C1:5

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