TDA9983BHW/15/C1:5 Datasheet TDA9983BHW/8/C1,55, TDA9983BHW/15/C1:5, TDA9983BHW/8/C1,51 | P88-P90

Product data sheet Rev. 01 — 20 May 2008 88 of 119

NXP Semiconductors

TDA9983B

150 MHz pixel rate HDMI transmitter

Table 95. ACR_N_x registers (address 08h to 0Ah) bit description

Legend: * = default value

Address Register Bit Symbol Access Value Description

0Ah ACR_N_2 7 to 4 x R/W 0000* undeﬁned

3 to 0 N[19:16] R/W 0000* N: audio clock recovery N value for

manual N-settings

09h ACR_N_1 7 to 0 N[15:8] R/W 60h*

08h ACR_N_0 7 to 0 N[7:0] R/W 00h*

Table 96. GC_AVMUTE register (address 0Bh) bit description

Legend: * = default value

Bit Symbol Access Value Description

7 to 2 x R/W 0000 00* undeﬁned

1 SET_MUTE R/W set mute: GCP.SB0 (bit 0)

0* no speciﬁc action

1 set AVMUTE ﬂag

0 CLR_MUTE R/W clear mute: GCP.SB0 (bit 4)

0* no speciﬁc action

1 clear AVMUTE ﬂag

Table 97. CTS_N register (address 0Ch) bit description

Legend: * = default value

Bit Symbol Access Value Description

7 to 6 x R/W 00* undeﬁned

5 to 4 M_SEL[1:0] R/W M select: postdivider mts (measured time

stamp)

00* CTS = mts

01 CTS = mts / 2

10 CTS = mts / 4

11 CTS = mts / 8

3 x R/W 0* undeﬁned

2 to 0 K_SEL[2:0] R/W K select: predivider (scales n)

000* k = 1

001 k = 2

010 k = 3

011 k = 4

1XX k = 8

Table 98. ENC_CNTRL register (address 0Dh) bit description

Legend: * = default value

Bit Symbol Access Value Description

7 to 4 x R/W 0000* undeﬁned

Product data sheet Rev. 01 — 20 May 2008 89 of 119

NXP Semiconductors

TDA9983B

150 MHz pixel rate HDMI transmitter

3 to 2 CTL_CODE[1:0] R/W control code: force CTL[1:0]

00 CTL[1:0] = 00 (DVI mode)

01* CTL[1:0] = 01 (advised to use in case of

HDMI mode)

10 CTL[1:0] = 10 (only for debugging purposes)

11 CTL[1:0] = 11 (only for debugging purposes)

1 to 0 DC_CTL[1:0] R/W disparity counter control

00* video guard band initializes disparity_cnt

01 video_data_enable enables disparity_cnt

10 free-running disparity_cnt

11 undeﬁned

Table 99. DIP_FLAGS register (address 0Eh) bit description

Legend: * = default value

Bit Symbol Access Value Description

7 FORCE_NULL R/W force null

0* no speciﬁc action

1 insert null-packets continuously

6 NULL R/W null

0* no speciﬁc action

1 insert one null-packet (this bit is reset by

internal control)

5 - R/W -: data packet header/contents as speciﬁed by

registers 80h to 9Eh

0* no speciﬁc action

1 insert InfoFrame in ﬁrst free slot after the

keepout window

4 ACP R/W audio content protection: data packet

header/contents as speciﬁed by registers 60h

to 7Eh (see

Table 105)

0* no speciﬁc action

1 insert ’acp’ in ﬁrst free slot after the keepout

window

3 ISRC2 R/W international standard recording code 2:

data packet header/contents as speciﬁed by

registers 40h to 5Eh (see

Table 104)

0* no speciﬁc action

1 insert ’isrc2’ in ﬁrst free slot after the keepout

window

Table 98. ENC_CNTRL register (address 0Dh) bit description

…continued

Legend: * = default value

Bit Symbol Access Value Description

Product data sheet Rev. 01 — 20 May 2008 90 of 119

NXP Semiconductors

TDA9983B

150 MHz pixel rate HDMI transmitter

2 ISRC1 R/W international standard recording code 1:

data packet header/contents as speciﬁed by

registers 20h to 3Eh (see

Table 103)

0* no speciﬁc action

1 insert ’isrc1’ in ﬁrst free slot after the keepout

window

1 GC R/W general control

0* no speciﬁc action

1 insert general control packet (just after

v-pulse)

0 ACR R/W audio clock regeneration

0* no speciﬁc action

1 insert audio clock regeneration packets

Table 100. DIP_IF_FLAGS register (address 0Fh) bit description

Legend: * = default value

Bit Symbol Access Value Description

7 to 6 x R/W 00* undeﬁned

5 IF5 R/W if5: data packet header/contents as speciﬁed

by registers A0h to BEh (page 10h)

0* no speciﬁc action

1 insert ’if5’ in ﬁrst free slot after the keepout

window

4 IF4 R/W if4: data packet header/contents as speciﬁed

by registers 80h to 9Eh (page 10h)

0* no speciﬁc action

1 insert ’if4’ in ﬁrst free slot after the keepout

window

3 IF3 R/W if3: data packet header/contents as speciﬁed

by registers 60h to 7Eh (page 10h)

0* no speciﬁc action

1 insert ’if3’ in ﬁrst free slot after the keepout

window

2 IF2 R/W if2: data packet header/contents as speciﬁed

by registers 40h to 5Eh (page 10h)

0* no speciﬁc action

1 insert ’if2’ in ﬁrst free slot after the keepout

window

1 IF1 R/W if1: data packet header/contents as speciﬁed

by registers 20h to 3Eh (page 10h)

0* no speciﬁc action

1 insert ’if1’ in ﬁrst free slot after the keepout

window

0 x R/W 0* undeﬁned

Table 99. DIP_FLAGS register (address 0Eh) bit description

…continued

Legend: * = default value

Bit Symbol Access Value Description

TDA9983BHW/15/C1:5

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