TDA9983BHW/15/C1:5 Datasheet TDA9983BHW/8/C1,55, TDA9983BHW/15/C1:5, TDA9983BHW/8/C1,51 | P22-P24

Product data sheet Rev. 01 — 20 May 2008 22 of 119

NXP Semiconductors

TDA9983B

150 MHz pixel rate HDMI transmitter

• Embedded deinterlacer (no need for output memory)

• Maximum output operating frequency: 74.5 MHz (HDTV supported 1080i, 720p)

• Input video standards (YC

4 : 2 : 2 semi-planar, ITU656 and ITU656-like YC

no RGB and no YC

4:4:4)

8.16 Input and output video scaler

The scaler converts the standard deﬁnition video signals (480i/576i, 480p/576p) into

720p, 1080i as illustrated in Figure 12.

8.17 I

C-bus interface

The I

C-bus pins I2C_SDA and I2C_SCL are 5 V tolerant and can work at fast mode

(400 kHz).

All upscaling modes are available only for YC

4 : 2 : 2 input format.

(1) Pass through

(2) Upscaling

(3) Upscaling and interlacing

(4) Deinterlacing

(5) Deinterlacing and upscaling

(6) Deinterlacing, upscaling and interlacing

Fig 12. Input and output video scaler

001aag258

720

1280

1920

720

1920

480p

720p

1080i

480i

1080p

2, 3

6, 7 (NTSC)

720

1280

1920

720

1920

576p

720p

1080i

576i

1080p

480p

720p

1080i

480i

1080p

720

1280

1920

720

1920

576p

720p

1080i

576i

1080p

720

1280

1920

720

1920

17, 18

21, 22 (PAL)

2, 3

6, 7 (NTSC)

17, 18

21, 22 (PAL)

VIDEO STANDARD OUTPUT

VIDEO STANDARD INPUT

FORMAT

861B

FORMAT

861B

(1)

(2)

(3)

(1)

(6)

(5)

(4)

(1)

Product data sheet Rev. 01 — 20 May 2008 23 of 119

NXP Semiconductors

TDA9983B

150 MHz pixel rate HDMI transmitter

9. I

C-bus register deﬁnitions

9.1 I

C-bus protocol

The registers of the TDA9983B can be accessed via the I

C-bus. The TDA9983B is used

as a slave device and both the fast mode 400 kHz and the standard mode 100 kHz are

supported.

Bits A0 and A1 of the I

C-bus device address are externally selected by pins A0 and A1.

The I

C-bus device address is given in Table 17.

The I

C-bus access format is shown in Figure 13.

For read access, the master writes the address of the TDA9983B, the subaddress to

access the speciﬁc register and then the data.

9.2 Memory page management

The I

C-bus memory is split into several pages and the selection between pages is made

with common register CURPAGE_ADR. It is only necessary to write in this register once

to change the current page. So multiple read or write operations in the same page need a

write register CURPAGE_ADR once at the beginning.

9.3 General control page register deﬁnitions

The current page address for the general control page is 00h.

The conﬁguration of the registers for this page is given in Table 19.

Table 17. Device address

Device address R/W

A6 A5 A4 A3 A2 A1 A0 -

1 1 1 0 0 A1 A0 1/0

Fig 13. I

C-bus access

001aaf292

123456789123456789123456789

SLAVE ADDRESS SUBADDRESS

SCL

SDA

DATA STOP

Table 18. Memory pages

Page address Memory page description Reference

00h General control see

Section 9.3 on page 23

01h Scaler see

Section 9.4 on page 43

02h PLL settings see

Section 9.5 on page 55

10h Information frames and packets see

Section 9.6 on page 63

11h Audio settings and content info packets see

Section 9.7 on page 81

12h HDMI and DVI see

Section 9.8 on page 98

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Product data sheet Rev. 01 — 20 May 2008 24 of 119

NXP Semiconductors

TDA9983B

150 MHz pixel rate HDMI transmitter

Table 19. I

C-bus registers of memory page 00h

[1]

addr

R/W Bit Default

value

7 (MSB) 6 5 4 3 2 1 0 (LSB)

VERSION 00h R 0 1 1000100110 0010

MAIN_CNTRL0 01h W SCALER x x CEHS CECS DEHS DECS SR 0000 0000

Not used 02h - - 0000 0000

::: : :

Not used 0Eh - - 0000 0000

INT_FLAGS_0 0Fh R/W x x xxxxHPDx0000 0000

INT_FLAGS_1 10h R/W HPD_IN x SC_DEIL SC_VID SC_OUT SC_IN x VS_RPT 0000 0000

Not used 11h - - 0000 0000

::: : :

Not used 1Fh - - 0000 0000

VIP_CNTRL_0 20h W MIRR_A SWAP_A[2:0] MIRR_B SWAP_B[2:0] 0000 0001

VIP_CNTRL_1 21h W MIRR_C SWAP_C[2:0] MIRR_D SWAP_D[2:0] 0010 0100

VIP_CNTRL_2 22h W MIRR_E SWAP_E[2:0] MIRR_F SWAP_F[2:0] 0101 0110

VIP_CNTRL_3 23h W EDGE x SP_SYNC[1:0] EMB V_TGL H_TGL X_TGL 0001 0110

VIP_CNTRL_4 24h W TST_PAT TST_656 x CCIR656 BLANKIT[1:0] BLC[1:0] 0000 0001

VIP_CNTRL_5 25h W x x x x x SP_CNT[1:0] CKCASE 0000 0000

Not used 26h - - 0000 0000

::: : :

Not used 7Fh - - 0000 0000

MAT_CONTRL 80h W x x x x x MAT_BP MAT_SC[1:0] 0000 0101

MAT_OI1_MSB 81h W x x x x x OFFSET_IN1[10:8] 0000 0000

MAT_OI1_LSB 82h W OFFSET_IN1[7:0] 0000 0000

MAT_OI2_MSB 83h W x x x x x OFFSET_IN2[10:8] 0000 0110

MAT_OI2_LSB 84h W OFFSET_IN2[7:0] 0000 0000

MAT_OI3_MSB 85h W x x x x x OFFSET_IN3[10:8] 0000 0110

MAT_OI3_LSB 86h W OFFSET_IN3[7:0] 0000 0000

MAT_P11_MSB 87h W x x x x x P11[10:8] 0000 0010

MAT_P11_LSB 88h W P11[7:0] 0000 0000

MAT_P12_MSB 89h W x x x x x P12[10:8] 0000 0110

MAT_P12_LSB 8Ah W P12[7:0] 1001 0010

MAT_P13_MSB 8Bh W x x x x x P13[10:8] 0000 0111

MAT_P13_LSB 8Ch W P13[7:0] 0101 0000

TDA9983BHW/15/C1:5

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