TDA9983B_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 20 May 2008 42 of 119
NXP Semiconductors
TDA9983B
150 MHz pixel rate HDMI transmitter
9.3.7 Timer control registers
9.3.8 NDIV register
9.3.9 Control registers
Table 47. Timer control registers (address E8h to EAh) bit description
Legend: * = default value
Address Register Bit Symbol Access Value Description
E8h TIMER_H 7 IM_CLKSEL W im timer clock select
0 ddc_master clocked by
hdmi_clk / (NDIV_IM[3:0] + 1)
1 ddc_master clocked by
cclk / 3 (typically 10 MHz)
6 WD_CLKSEL W watchdog timer clock select
0 wd_timer clocked by
hdmi_clk / (NDIV_PF[7:0] + 1)
1 wd_timer clocked by cclk / 32
5 to 2 x W 0000* undefined
1 to 0 TIM_H[1:0] W timer control register height
00 tim[17:16] = ’00’
01* tim[17:16] = ’01’
10 tim[17:16] = ’10’
00 tim[17:16] = ’11’
E9h TIMER_M 7 to 0 TIM_M[7:0] W timer control register medium
C2h* tim[15:8] = TIM_M[7:0]
EAh TIMER_L 7 to 0 TIM_L[7:0] W timer control register low
40h* tim[7:0] = TIM_L[7:0]
Table 48. NDIV_xxx registers (address EEh and EFh) bit description
Legend: * = default value
Address Register Bit Symbol Access Value Description
EEh NDIV_IM 7 to 4 x W 0000* undefined
3 to 0 NDIV_IM[3:0] W N divisor DDC-bus master
0011* N divisor to set clock period for
DDC-bus master
EFh NDIV_PF 7 to 0 NDIV_PF[7:0] W N divisor pixel frequency
1Bh* N divisor to set clock period for timers
(equals pixel frequency)
Table 49. Control registers (address F0h to F2h, F9h, FDh and FEh) bit description
Legend: * = default value
Address Register Bit Symbol Access Value Description
F0h RPT_CNTRL 7 to 4 x W 0000* undefined
3 to 0 REPEAT[3:0] W 0000* repeat: repeater control
F1h LEAD_OFF 7 to 4 x W 0000* undefined
3 to 0 LEAD_OFFSET[3:0] W 0010* leading offset: leading offset for dwin
(in case rpt > 1)
