TDA9983BHW/15/C1:5 Datasheet TDA9983BHW/8/C1,55, TDA9983BHW/15/C1:5, TDA9983BHW/8/C1,51 | P52-P54

Product data sheet Rev. 01 — 20 May 2008 52 of 119

NXP Semiconductors

TDA9983B

150 MHz pixel rate HDMI transmitter

32h SC_VS_LUT_23 7 to 0 VS_LUT23[7:0] W - vertical scaler LUT 23: external LUT

coefﬁcient[23] for vertical scaler

33h SC_VS_LUT_24 7 to 0 VS_LUT24[7:0] W - vertical scaler LUT 24: external LUT

coefﬁcient[24] for vertical scaler

34h SC_VS_LUT_25 7 to 0 VS_LUT25[7:0] W - vertical scaler LUT 25: external LUT

coefﬁcient[25] for vertical scaler

35h SC_VS_LUT_26 7 to 0 VS_LUT26[7:0] W - vertical scaler LUT 26: external LUT

coefﬁcient[26] for vertical scaler

36h SC_VS_LUT_27 7 to 0 VS_LUT27[7:0] W - vertical scaler LUT 27: external LUT

coefﬁcient[27] for vertical scaler

37h SC_VS_LUT_28 7 to 0 VS_LUT28[7:0] W - vertical scaler LUT 28: external LUT

coefﬁcient[28] for vertical scaler

38h SC_VS_LUT_29 7 to 0 VS_LUT29[7:0] W - vertical scaler LUT 29: external LUT

coefﬁcient[29] for vertical scaler

39h SC_VS_LUT_30 7 to 0 VS_LUT30[7:0] W - vertical scaler LUT 30: external LUT

coefﬁcient[30] for vertical scaler

3Ah SC_VS_LUT_31 7 to 0 VS_LUT31[7:0] W - vertical scaler LUT 31: external LUT

coefﬁcient[31] for vertical scaler

3Bh SC_VS_LUT_32 7 to 0 VS_LUT32[7:0] W - vertical scaler LUT 32: external LUT

coefﬁcient[32] for vertical scaler

3Ch SC_VS_LUT_33 7 to 0 VS_LUT33[7:0] W - vertical scaler LUT 33: external LUT

coefﬁcient[33] for vertical scaler

3Dh SC_VS_LUT_34 7 to 0 VS_LUT34[7:0] W - vertical scaler LUT 34: external LUT

coefﬁcient[34] for vertical scaler

3Eh SC_VS_LUT_35 7 to 0 VS_LUT35[7:0] W - vertical scaler LUT 35: external LUT

coefﬁcient[35] for vertical scaler

3Fh SC_VS_LUT_36 7 to 0 VS_LUT36[7:0] W - vertical scaler LUT 36: external LUT

coefﬁcient[36] for vertical scaler

40h SC_VS_LUT_37 7 to 0 VS_LUT37[7:0] W - vertical scaler LUT 37: external LUT

coefﬁcient[37] for vertical scaler

41h SC_VS_LUT_38 7 to 0 VS_LUT38[7:0] W - vertical scaler LUT 38: external LUT

coefﬁcient[38] for vertical scaler

42h SC_VS_LUT_39 7 to 0 VS_LUT39[7:0] W - vertical scaler LUT 39: external LUT

coefﬁcient[39] for vertical scaler

43h SC_VS_LUT_40 7 to 0 VS_LUT40[7:0] W - vertical scaler LUT 40: external LUT

coefﬁcient[40] for vertical scaler

44h SC_VS_LUT_41 7 to 0 VS_LUT41[7:0] W - vertical scaler LUT 41: external LUT

coefﬁcient[41] for vertical scaler

45h SC_VS_LUT_42 7 to 0 VS_LUT42[7:0] W - vertical scaler LUT 42: external LUT

coefﬁcient[42] for vertical scaler

46h SC_VS_LUT_43 7 to 0 VS_LUT43[7:0] W - vertical scaler LUT 43: external LUT

coefﬁcient[43] for vertical scaler

47h SC_VS_LUT_44 7 to 0 VS_LUT44[7:0] W - vertical scaler LUT 44: external LUT

coefﬁcient[44] for vertical scaler

Table 59. SC_VS_LUT_xx registers (address 1Bh to 47h) bit description

…continued

Legend: * = default value

Address Register Bit Symbol Access Value Description

Product data sheet Rev. 01 — 20 May 2008 53 of 119

NXP Semiconductors

TDA9983B

150 MHz pixel rate HDMI transmitter

9.4.2 Scaling input time base generator control registers

Table 60. VIDFORMAT register (address A0h) bit description

Legend: * = default value

Bit Symbol Access Value Description

7 to 3 x W 0000 0* undeﬁned

2 to 0 VIDFORMAT[2:0] W video format: time base generator for scaler

input formats

000* 480i 60 Hz

001 576i 50 Hz

010 480p 60 Hz

011 576p 50 Hz

1XX reserved for future use

Table 61. REFPIX_xx, REFLINE_xx, NPIX_xx and NLINE_xx registers (address A1h to A8h) bit description

Legend: * = default value

Address Register Bit Symbol Access Value Description

A1h REFPIX_MSB 7 to 2 x W 0000 00* undeﬁned

1 to 0 PRESET_PIX[9:8] W 00* preset pixel: reference pixel

preset

A2h REFPIX_LSB 7 to 0 PRESET_PIX[7:0] W 01h*

A3h REFLINE_MSB 7 to 2 x W 0000 00* undeﬁned

1 to 0 PRESET_LINE[9:8] W 00* preset line: reference line preset

A4h REFLINE_LSB 7 to 0 PRESET_LINE[7:0] W 01h*

A5h NPIX_MSB 7 to 2 x W 0000 00* undeﬁned

1 to 0 NPIX[9:8] W 00* number pixel: number of pixels

per line

A6h NPIX_LSB 7 to 0 NPIX[7:0] W 00h*

A7h NLINE_MSB 7 to 2 x W 0000 00* undeﬁned

1 to 0 NLINE[9:8] W 00* number line: number of lines per

frame

A8h NLINE_LSB 7 to 0 NLINE[7:0] W 00h*

Table 62. VWIN_START_x_xx and VWIN_END_x_xx registers (address BDh to C4h) bit description

Legend: * = default value

Address Register Bit Symbol Access Value Description

BDh VWIN_START_1_MSB 7 to 2 x W 0000 00* undeﬁned

1 to 0 VWIN_START_1[9:8] W 00* vertical window start 1: vertical

window line number for start

pulse in ﬁeld 1

BEh VWIN_START_1_LSB 7 to 0 VWIN_START_1[7:0] W 00h*

BFh VWIN_END_1_MSB 7 to 2 x W 0000 00* undeﬁned

1 to 0 VWIN_END_1[9:8] W 00* vertical window end 1: vertical

window line number for end pulse

in ﬁeld 1

C0h VWIN_END_1_LSB 7 to 0 VWIN_END_1[7:0] W 00h*

C1h VWIN_START_2_MSB 7 to 2 x W 0000 00* undeﬁned

1 to 0 VWIN_START_2[9:8] W 00* vertical window start 2: vertical

window line number for start

pulse in ﬁeld 2

C2h VWIN_START_2_LSB 7 to 0 VWIN_START_2[7:0] W 00h*

Product data sheet Rev. 01 — 20 May 2008 54 of 119

NXP Semiconductors

TDA9983B

150 MHz pixel rate HDMI transmitter

C3h VWIN_END_2_MSB 7 to 2 x W 0000 00* undeﬁned

1 to 0 VWIN_END_2[9:8] W 00* vertical window end 2: vertical

window line number for end pulse

in ﬁeld 2

C4h VWIN_END_2_LSB 7 to 0 VWIN_END_2[7:0] W 00h*

Table 62. VWIN_START_x_xx and VWIN_END_x_xx registers (address BDh to C4h) bit description

…continued

Legend: * = default value

Address Register Bit Symbol Access Value Description

Table 63. DE_START_x and DE_STOP_x registers (address C5h to C8h) bit description

Legend: * = default value

Address Register Bit Symbol Access Value Description

C5h DE_START_MSB 7 to 2 x W 0000 00* undeﬁned

1 to 0 DE_START[9:8] W 00* data enable start: data enable

pixel number for start pulse in

ﬁeld 1

C6h DE_START_LSB 7 to 0 DE_START[7:0] W 00h*

C7h DE_STOP_MSB 7 to 2 x W 0000 00* undeﬁned

1 to 0 DE_END[9:8] W 00* data enable end: data enable

pixel number for end pulse in

ﬁeld 2

C8h DE_STOP_LSB 7 to 0 DE_END[7:0] W 00h*

Table 64. TBG_CNTRL_0 register (address CAh) bit description

Legend: * = default value

Bit Symbol Access Value Description

7 SYNC_ONCE W sync once

0* line/pixel counters are synchronized each

frame

1 line/pixel counters are synchronized only

once

6 SYNC_MTHD W sync method

0* synchronization is based on combination of

v and h

1 synchronization is based on combination of

v and x (de)

5 FRAME_DIS W frame disable: synchronized by linecnt = 1

AND pixelcnt = 1

0* enable video frames

1 disable video frames

4 x W 0* undeﬁned

3 TOP_EXT W top external

0* top = top_tbg_sci

1 top = x_vip (external; fref)

2 DE_EXT W data enable external

0* de = de_tbg_sci (internal)

1 de = x_vip (external; de)

TDA9983BHW/15/C1:5

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TDA9983BHW/15/C1:5

TDA9983BHW/15/C1:5

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