TDA9983BHW/8/C1,51 Datasheet TDA9983BHW/8/C1,55, TDA9983BHW/15/C1:5, TDA9983BHW/8/C1,51 | P103-P105

Product data sheet Rev. 01 — 20 May 2008 103 of 119

NXP Semiconductors

TDA9983B

150 MHz pixel rate HDMI transmitter

13. Dynamic characteristics

Table 115. Timing characteristics

DDA(FRO_3V3)

= 3.0 V to 3.6 V; V

DDA(PLL_3V3)

= 3.0 V to 3.6 V; V

DDH(3V3)

= 3.0 V to 3.6 V; V

DDD(3V3)

= 3.0 V to 3.6 V;

DDC(1V8)

= 1.65 V to 1.95 V; V

= 0 V; T

amb

= 0

C to 70

Typical values are measured at V

DDA(FRO_3V3)

= V

DDA(PLL_3V3)

= V

DDH(3V3)

= V

DDD(3V3)

= 3.3 V; V

DDC(1V8)

= 1.8 V; V

= 0 V

and T

amb

= 25

C; unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Supplies: pins V

DDC(1V8)

, V

DDD(3V3)

; see Figure 14

delay time 1 - - ms

Clock inputs: pins VCLK, VPA[7:0], VPB[7:0], VPC[7:0]; see

Figure 15, 16, 17, 18 and 19

clk(max)

maximum clock frequency TDA9983BHW/8 81 - - MHz

TDA9983BHW/15 150 - - MHz

su(D)

data input set-up time −1.3 - - ns

h(D)

data input hold time 3.6 - - ns

clk

clock duty cycle 40 - 60 %

DDC I

C-bus; 5 V tolerant; master bus: pins DDC_SDA and DDC_SCL

SCL

SCL clock frequency standard mode - - 100 kHz

C-bus; 5 V tolerant; master bus: pins I2C_SDA and I2C_SCL

SCL

SCL clock frequency standard mode - - 100 kHz

fast mode - - 400 kHz

TMDS output pins: TXC− and TXC+

clk(max)

maximum clock frequency TDA9983BHW/8 81 - - MHz

TDA9983BHW/15 150 - - MHz

TMDS output pins: TX0−, TX0+, TX1−, TX1+, TX2− and TX2+

clk(max)

maximum clock frequency TDA9983BHW/8 810 - - MHz

TDA9983BHW/15 1.5 - - GHz

Fig 14. Power supply sequencing

001aag259

50 % 27 %

≥ 0 s

1.8 V

3.3 V

Product data sheet Rev. 01 — 20 May 2008 104 of 119

NXP Semiconductors

TDA9983B

150 MHz pixel rate HDMI transmitter

13.1 Input format

In Table 116 the port VPA has been mapped to C

(YUV space)/B (RGB space), VPB has

been mapped to Y (YUV space)/G (RGB space) and VPC has been mapped to C

(YUV

space)/R (RGB space).

[1] Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 45h; VIP_CNTRL_2 = 01h.

[2] Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 45h; VIP_CNTRL_2 = 01h.

[3] Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 14h.

[4] Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 00h.

Table 116. Input format

Input pins Signal RGB YUV

4:4:4

[1]

4:4:4

[2]

4:2:2 (semi-planar)

[3]

4 : 2 : 2: (ITU656-like)

[4]

Video port A

VPA[0] C

[0]/B[0] B[0] C

[0] Y

[0] C

[0] Y

[0] C

[0] Y

[0]

VPA[1] C

[1]/B[1] B[1] C

[1] Y

[1] C

[1] Y

[1] C

[1] Y

[1]

VPA[2] C

[2]/B[2] B[2] C

[2] Y

[2] C

[2] Y

[2] C

[2] Y

[2]

VPA[3] C

[3]/B[3] B[3] C

[3] Y

[3] C

[3] Y

[3] C

[3] Y

[3]

VPA[4] C

[4]/B[4] B[4] C

[4] C

[0] C

[0] LLLL

VPA[5] C

[5]/B[5] B[5] C

[5] C

[1] C

[1] LLLL

VPA[6] C

[6]/B[6] B[6] C

[6] C

[2] C

[2] LLLL

VPA[7] C

[7]/B[7] B[7] C

[7] C

[3] C

[3] LLLL

Video port B

VPB[0] Y[0]/G[0] G[0] Y[0] Y

[4] Y

[4] C

[4] Y

[4] C

[4] Y

[4]

VPB[1] Y[1]/G[1] G[1] Y[1] Y

[5] Y

[5] C

[5] Y

[5] C

[5] Y

[5]

VPB[2] Y[2]/G[2] G[2] Y[2] Y

[6] Y

[6] C

[6] Y

[6] C

[6] Y

[6]

VPB[3] Y[3]/G[3] G[3] Y[3] Y

[7] Y

[7] C

[7] Y

[7] C

[7] Y

[7]

VPB[4] Y[4]/G[4] G[4] Y[4] Y

[8] Y

[8] C

[8] Y

[8] C

[8] Y

[8]

VPB[5] Y[5]/G[5] G[5] Y[5] Y

[9] Y

[9] C

[9] Y

[9] C

[9] Y

[9]

VPB[6] Y[6]/G[6] G[6] Y[6] Y

[10] Y

[10] C

[10] Y

[10] C

[10] Y

[10]

VPB[7] Y[7]/G[7] G[7] Y[7] Y

[11] Y

[11] C

[11] Y

[11] C

[11] Y

[11]

Video port C

VPC[0] C

[0]/R[0] R[0] C

[0] C

[4] C

[4] LLLL

VPC[1] C

[1]/R[1] R[1] C

[1] C

[5] C

[5] LLLL

VPC[2] C

[2]/R[2] R[2] C

[2] C

[6] C

[6] LLLL

VPC[3] C

[3]/R[3] R[3] C

[3] C

[7] C

[7] LLLL

VPC[4] C

[4]/R[4] R[4] C

[4] C

[8] C

[8] LLLL

VPC[5] C

[5]/R[5] R[5] C

[5] C

[9] C

[9] LLLL

VPC[6] C

[6]/R[6] R[6] C

[6] C

[10] C

[10] L L L L

VPC[7] C

[7]/R[7] R[7] C

[7] C

[11] C

[11] L L L L

Product data sheet Rev. 01 — 20 May 2008 105 of 119

NXP Semiconductors

TDA9983B

150 MHz pixel rate HDMI transmitter

13.2 Example of supported video

The TDA9983B supports all EIA/CEA-861B, ATSC video input formats.

Table 117. Timing parameters for EIA/CEA-861B

Format nr. Format V frequency

(Hz)

H total V total H frequency

(kHz)

Pixel frequency

(MHz)

Pixel repetition Scaler

59.94 Hz systems

1 (VGA) 640 × 480p 59.9401 800 525 31.4685 25.174825 1 -

2, 3 720 × 480p 59.9401 858 525 31.4685 27 1 X

4 1280 × 720p 59.9401 1650 750 44.955 74.175824 1 -

5 1920 × 1080i 59.9401 2200 1125 33.7163 74.175824 1 -

6, 7 (NTSC) 720 × 480i 59.9401 858 525 15.7343 13.5 2 X

8, 9 720 × 240p 59.9401 858 262 15.7043 13.474286 2 -

8, 9 720 × 240p 59.9401 858 263 15.7642 13.525714 2 -

10, 11 720 × 480i 59.9401 858 525 15.7343 13.5 4, 5, 7

[1]

, 8

[1]

12, 13 720 × 240p 59.9401 858 262 15.7043 13.474286 4, 5, 7

[1]

, 8

[1]

12, 13 720 × 240p 59.9401 858 263 15.7642 13.525714 4, 5, 7

[1]

, 8

[1]

14, 15 1440 × 480p 59.9401 1716 525 31.4685 54 2 -

[1]

1920 × 1080p 59.9401 2200 1125 67.4326 148.35165

[1]

60 Hz systems

1 (VGA) 640 × 480p 60 800 525 31.5 25.2 1 -

2, 3 720 × 480p 60 858 525 31.5 27.27 1 X

4 1280 × 720p 60 1650 750 45 74.25 1 -

5 1920 × 1080i 60 2200 1125 33.75 74.25 1 -

6, 7 (NTSC) 720 × 480i 60 858 525 15.75 13.5135 2 X

8, 9 720 × 240p 60 858 262 15.72 13.48776 2 -

8, 9 720 × 240p 60 858 263 15.78 13.53924 2 -

10, 11 720 × 480i 60 858 525 15.75 13.5135 4, 5, 7

[1]

, 8

[1]

12, 13 720 × 240p 60 858 262 15.72 13.48776 4, 5, 7

[1]

, 8

[1]

12, 13 720 × 240p 60 858 263 15.78 13.53924 4, 5, 7

[1]

, 8

[1]

14, 15 1440 × 480p 60 1716 525 31.5 54.054 2 -

[1]

1920 × 1080p 60 2200 1125 67.5 148.5

[1]

50 Hz systems

17, 18 720 × 576p 50 864 625 31.25 27 1 X

19 1280 × 720p 50 1980 750 37.5 74.25 1 -

20 1920 × 1080i 50 2640 1125 28.125 74.25 1 -

21, 22 (PAL) 720 × 576i 50 864 625 15.625 13.5 1 X

23, 24 720 × 288p 50 864 312 15.6 13.4784 2 -

23, 24 720 × 288p 50 864 313 15.65 13.5216 2 -

TDA9983BHW/8/C1,51

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NXP Semiconductors

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IC HDMI TX 81MHZ 80-HTQFP

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TDA9983BHW/8/C1,51

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