TDA9983B_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 20 May 2008 16 of 119
NXP Semiconductors
TDA9983B
150 MHz pixel rate HDMI transmitter
Table 12. YC
B
C
R
4:2:2 semi-planar external synchronization mappings
YC
B
C
R
4:2:2 semi-planar external synchronization single edge.
Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 14h.
Video port A Video port B Video port C Control
Pin YC
B
C
R
4:2:2
semi-planar
Pin YC
B
C
R
4:2:2
semi-planar
Pin YC
B
C
R
4:2:2
semi-planar
Pin YC
B
C
R
4:2:2
VPA[0] Y
0
[0] Y
1
[0] VPB[0] Y
0
[4] Y
1
[4] VPC[0] C
B
[4] C
R
[4] HSYNC/HREF used
VPA[1] Y
0
[1] Y
1
[1] VPB[1] Y
0
[5] Y
1
[5] VPC[1] C
B
[5] C
R
[5] VSYNC/VREF used
VPA[2] Y
0
[2] Y
1
[2] VPB[2] Y
0
[6] Y
1
[6] VPC[2] C
B
[6] C
R
[6] DE/FREF used
VPA[3] Y
0
[3] Y
1
[3] VPB[3] Y
0
[7] Y
1
[7] VPC[3] C
B
[7] C
R
[7]
VPA[4] C
B
[0] C
R
[0] VPB[4] Y
0
[8] Y
1
[8] VPC[4] C
B
[8] C
R
[8]
VPA[5] C
B
[1] C
R
[1] VPB[5] Y
0
[9] Y
1
[9] VPC[5] C
B
[9] C
R
[9]
VPA[6] C
B
[2] C
R
[2] VPB[6] Y
0
[10] Y
1
[10] VPC[6] C
B
[10] C
R
[10]
VPA[7] C
B
[3] C
R
[3] VPB[7] Y
0
[11] Y
1
[11] VPC[7] C
B
[11] C
R
[11]
Fig 9. Pixel encoding YC
B
C
R
4 : 2 : 2 semi-planar external synchronization (rising edge) input
001aag386
Y5 ...Y4Y3Y2Y1Y0
HSYNC/HREF
VSYNC/VREF
DE/FREF
C
R
4 ...C
B
4C
R
2C
B
2C
R
0C
B
0
CONTROL
INPUTS
VPB[7:0]; VPA[3:0]
VCLK
VPC[7:0]; VPA[7:4]
TDA9983B_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 20 May 2008 17 of 119
NXP Semiconductors
TDA9983B
150 MHz pixel rate HDMI transmitter
Table 13. YC
B
C
R
4:2:2 semi-planar embedded synchronization mappings
YC
B
C
R
4:2:2 semi-planar embedded synchronization single edge.
Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 14h.
Video port A Video port B Video port C Control
Pin YC
B
C
R
4:2:2
semi-planar
Pin YC
B
C
R
4:2:2
semi-planar
Pin YC
B
C
R
4:2:2
semi-planar
Pin YC
B
C
R
4:2:2
VPA[0] Y
0
[0] Y
1
[0] VPB[0] Y
0
[4] Y
1
[4] VPC[0] C
B
[4] C
R
[4] HSYNC/HREF not used
VPA[1] Y
0
[1] Y
1
[1] VPB[1] Y
0
[5] Y
1
[5] VPC[1] C
B
[5] C
R
[5] VSYNC/VREF not used
VPA[2] Y
0
[2] Y
1
[2] VPB[2] Y
0
[6] Y
1
[6] VPC[2] C
B
[6] C
R
[6] DE/FREF not used
VPA[3] Y
0
[3] Y
1
[3] VPB[3] Y
0
[7] Y
1
[7] VPC[3] C
B
[7] C
R
[7]
VPA[4] C
B
[0] C
R
[0] VPB[4] Y
0
[8] Y
1
[8] VPC[4] C
B
[8] C
R
[8]
VPA[5] C
B
[1] C
R
[1] VPB[5] Y
0
[9] Y
1
[9] VPC[5] C
B
[9] C
R
[9]
VPA[6] C
B
[2] C
R
[2] VPB[6] Y
0
[10] Y
1
[10] VPC[6] C
B
[10] C
R
[10]
VPA[7] C
B
[3] C
R
[3] VPB[7] Y
0
[11] Y
1
[11] VPC[7] C
B
[11] C
R
[11]
Fig 10. Pixel encoding YC
B
C
R
4 : 2 : 2 semi-planar embedded synchronization (rising edge) input
001aag387
Y5 ...Y4Y3Y2Y1Y0
C
R
4 ...C
B
4C
R
2C
B
2C
R
0C
B
0
VPB[7:0]; VPA[3:0]
VCLK
VPC[7:0]; VPA[7:4]
TDA9983B_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 20 May 2008 18 of 119
NXP Semiconductors
TDA9983B
150 MHz pixel rate HDMI transmitter
8.3 Synchronization
The TDA9983B can be synchronized with Hsync/Vsync external inputs or with extraction
of the sync information from embedded sync (SAV/EAV) codes inside the video stream.
8.3.1 Timing extraction generator
This block can extract the synchronization signals Href, Vref and Fref from Start Active
Video (SAV) and End Active Video (EAV) in case of embedded synchronization in the data
stream. Synchronization signals can be embedded in RGB, YC
B
C
R
4 : 4 : 4, YC
B
C
R
4:2:2 semi-planar (up to 2 × 12-bit), YC
B
C
R
4:2:2 ITU656 and ITU656-like (up to
1 × 12-bit).
8.3.2 Data enable generator
The TDA9983B contains a Data Enable (DE) generator; this can generate an internal DE
signal for a system which does not provide one.
8.4 Input and output video format
Due to the flexible video input formatter, the TDA9983B can accept a large range of input
formats. This flexibility allows the TDA9983B to be compatible with the maximum possible
number of MPEG decoders. Moreover, these input formats may be changed in many ways
(color space converter, upsampler, downsampler and scaler) to be transmitted across the
HDMI link. Table 14 gives the possible inputs and outputs.
8.5 Upsampler
The incoming YC
B
C
R
4 : 2 : 2 (2 × 12-bit) data stream format could be upsampled into a
12-bit YC
B
C
R
4 : 4 : 4 (3 × 12-bit) data stream by repeating or linearly interpolating the
chrominance pixels.
Table 14. Use of color space converter, upsampler, downsampler and scaler
Input Scaler Output
Color space Format Channels Color space Format Channels
RGB 4:4:4 3× 8-bit no scaling RGB 4:4:4 3× 8-bit
no scaling YC
B
C
R
4:2:2 2× 12-bit
no scaling YC
B
C
R
4:4:4 3× 8-bit
YC
B
C
R
4:4:4 3× 8-bit no scaling RGB 4:4:4 3× 8-bit
no scaling YC
B
C
R
4:2:2 2× 12-bit
no scaling YC
B
C
R
4:4:4 3× 8-bit
YC
B
C
R
4 : 2 : 2 up to 1 × 12-bit scalable YC
B
C
R
4:2:2 2× 12-bit
scalable YC
B
C
R
4:4:4 3× 8-bit
scalable RGB 4:4:4 3× 8-bit
up to 2 × 12-bit scalable YC
B
C
R
4:2:2 2× 12-bit
scalable YC
B
C
R
4:4:4 3× 8-bit
scalable RGB 4:4:4 3× 8-bit

TDA9983BHW/8/C1,51

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
IC HDMI TX 81MHZ 80-HTQFP
Lifecycle:
New from this manufacturer.
Delivery:
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