TDA9983BHW/8/C1,51 Datasheet TDA9983BHW/8/C1,55, TDA9983BHW/15/C1:5, TDA9983BHW/8/C1,51 | P34-P36

Product data sheet Rev. 01 — 20 May 2008 34 of 119

NXP Semiconductors

TDA9983B

150 MHz pixel rate HDMI transmitter

9.3.4 Color space conversion registers

[1] The value is a signed 11-bit two’s complement integer.

0 CKCASE W ckcase

0* no speciﬁc action

1 toggle clk1case (phase clk1 with respect to

clk2)

Table 29. VIP_CNTRL_5 register (address 25h) bit description

…continued

Legend: * = default value

Bit Symbol Access Value Description

Table 30. MAT_CONTRL register (address 80h) bit description

Legend: * = default value

Bit Symbol Access Value Description

7 to 3 x W 0000 0* undeﬁned

2 MAT_BP W matrix bypassed: bypasses or not the matrix and

offsets

0 uses color space conversion

1* bypasses

1 and 0 MAT_SC[1:0] W matrix scale factor selection: sets the scale

factor to convert the ﬂoating matrix [C

] into an

integer matrix [P

The choice depends on the biggest coefﬁcient in

absolute value |C

00 when 2 ≤|C

| < 4; S = 256

01* when 1 ≤|C

| < 2; S = 512

10 when |C

| < 1; S = 1024

11 undeﬁned

INT S

×()=

Table 31. Offset input registers (address 81h to 86h) bit description

Legend: * = default value

Address Register Bit Symbol Access Value Description

81h MAT_OI1_MSB 7 to 3 x W 0000 0* undeﬁned

2 to 0 OFFSET_IN1[10:8] W 000* offset input 1: compensates the

brightness value for the G/Y channel

[1]

82h MAT_OI1_LSB 7 to 0 OFFSET_IN1[7:0] W 00h*

83h MAT_OI2_MSB 7 to 3 x W 0000 0* undeﬁned

2 to 0 OFFSET_IN2[10:8] W 110* offset input 2: compensates the

brightness value for the R/C

channel

[1]

84h MAT_OI2_LSB 7 to 0 OFFSET_IN2[7:0] W 00h*

85h MAT_OI3_MSB 7 to 3 x W 0000 0* undeﬁned

2 to 0 OFFSET_IN3[10:8] W 110* offset input 3: compensates the

brightness value for the B/C

channel

[1]

86h MAT_OI3_LSB 7 to 0 OFFSET_IN3[7:0] W 00h*

Product data sheet Rev. 01 — 20 May 2008 35 of 119

NXP Semiconductors

TDA9983B

150 MHz pixel rate HDMI transmitter

[1] The value is a signed 11-bit two’s complement integer.

Table 32. Coefﬁcient registers (address 87h to 98h) bit description

Legend: * = default value

Address Register Bit Symbol Access Value Description

87h MAT_P11_MSB 7 to 3 x W 0000 0* undeﬁned

2 to 0 P11[10:8] W 010* coefﬁcient (1, 1): coefﬁcient from the

G/Y channel to the G/Y channel

[1]

88h MAT_P11_LSB 7 to 0 P11[7:0] W 00h*

89h MAT_P12_MSB 7 to 3 x W 0000 0* undeﬁned

2 to 0 P12[10:8] W 110* coefﬁcient (1, 2): coefﬁcient from the

R/C

channel to the G/Y channel

[1]

8Ah MAT_P12_LSB 7 to 0 P12[7:0] W 92h*

8Bh MAT_P13_MSB 7 to 3 x W 0000 0* undeﬁned

2 to 0 P13[10:8] W 111* coefﬁcient (1, 3): coefﬁcient from the

B/C

channel to the G/Y channel

[1]

8Ch MAT_P13_LSB 7 to 0 P13[7:0] W 50h*

8Dh MAT_P21_MSB 7 to 3 x W 0000 0* undeﬁned

2 to 0 P21[10:8] W 010* coefﬁcient (2, 1): coefﬁcient from the

G/Y channel to the R/C

channel

[1]

8Eh MAT_P21_LSB 7 to 0 P21[7:0] W 00h*

8Fh MAT_P22_MSB 7 to 3 x W 0000 0* undeﬁned

2 to 0 P22[10:8] W 010* coefﬁcient (2, 2): coefﬁcient from the

R/C

channel to the R/C

channel

[1]

90h MAT_P22_LSB 7 to 0 P22[7:0] W CEh*

91h MAT_P23_MSB 7 to 3 x W 0000 0* undeﬁned

2 to 0 P23[10:8] W 000* coefﬁcient (2, 3): coefﬁcient from the

B/C

channel to the R/C

channel

[1]

92h MAT_P23_LSB 7 to 0 P23[7:0] W 00h*

93h MAT_P31_MSB 7 to 3 x W 0000 0* undeﬁned

2 to 0 P31[10:8] W 010* coefﬁcient (3, 1): coefﬁcient from the

G/Y channel to the B/C

channel

[1]

94h MAT_P31_LSB 7 to 0 P31[7:0] W 00h*

95h MAT_P32_MSB 7 to 3 x W 0000 0* undeﬁned

2 to 0 P32[10:8] W 000* coefﬁcient (3, 2): coefﬁcient from the

R/C

channel to the B/C

channel

[1]

96h MAT_P32_LSB 7 to 0 P32[7:0] W 00h*

97h MAT_P33_MSB 7 to 3 x W 0000 0* undeﬁned

2 to 0 P33[10:8] W 011* coefﬁcient (3, 3): coefﬁcient from the

B/C

channel to the B/C

channel

[1]

98h MAT_P33_LSB 7 to 0 P33[7:0] W 8Ch*

Table 33. Offset output registers (address 99h to 9Eh) bit description

Legend: * = default value

Address Register Bit Symbol Access Value Description

99h MAT_OO1_MSB 7 to 3 x W 0000 0* undeﬁned

2 to 0 OFFSET_OUT1[10:8] W 000* offset output 1: new clamp level for the

G/Y channel

[1]

9Ah MAT_OO1_LSB 7 to 0 OFFSET_OUT1[7:0] W 00h*

9Bh MAT_OO2_MSB 7 to 3 x W 0000 0* undeﬁned

2 to 0 OFFSET_OUT2[10:8] W 000* offset output 2: new clamp level for the

R/C

channel

[1]

9Ch MAT_OO2_LSB 7 to 0 OFFSET_OUT2[7:0] W 00h*

Product data sheet Rev. 01 — 20 May 2008 36 of 119

NXP Semiconductors

TDA9983B

150 MHz pixel rate HDMI transmitter

[1] The value is a signed 11-bit two’s complement integer.

9.3.5 Video format registers

9Dh MAT_OO3_MSB 7 to 3 x W 0000 0* undeﬁned

2 to 0 OFFSET_OUT3[10:8] W 000* offset output 3: new clamp level for the

B/C

channel

[1]

9Eh MAT_OO3_LSB 7 to 0 OFFSET_OUT3[7:0] W 00h*

Table 33. Offset output registers (address 99h to 9Eh) bit description

…continued

Legend: * = default value

Address Register Bit Symbol Access Value Description

Table 34. VIDFORMAT register (address A0h) bit description

Legend: * = default value

Bit Symbol Access Value Description

7 to 5 x W 000* undeﬁned

4 to 0 VIDFORMAT[4:0] W video format: see

EIA/CEA-861B speciﬁcation

0 0000* 640 × 480p at 60 Hz (format 1 (VGA))

0 0001 720 × 480p at 60 Hz (format 2/3)

0 0010 1280 × 720p at 60 Hz (format 4)

0 0011 1920 × 1080i at 60 Hz (format 5)

0 0100 720 × 480i at 60 Hz (format 6/7)

0 0101 720 × 240p at 60 Hz (format 8/9)

0 0110 1920 × 1080p at 60 Hz (format 16)

0 0111 720 × 576p at 50 Hz (format 17/18)

0 1000 1280 × 720p at 50 Hz (format 19)

0 1001 1920 × 1080i at 50 Hz (format 20)

0 1010 720 × 576i at 50 Hz (format 21/22)

0 1011 720 × 288p at 50 Hz (format 23/24)

others 1920 × 1080p at 50 Hz (format 31)

Table 35. REFPIX_xxx, REFLINE_xxx, NPIX_xxx and NLINE_xxx registers (address A1h to A8h) bit description

Legend: * = default value

Address Register Bit Symbol Access Value Description

A1h REFPIX_MSB 7 to 5 x W 000* undeﬁned

4 to 0 PRESET_PIX[12:8] W 0 0000* preset pixel: reference pixel

preset

A2h REFPIX_LSB 7 to 0 PRESET_PIX[7:0] W 01h*

A3h REFLINE_MSB 7 to 3 x W 0000 0* undeﬁned

2 to 0 PRESET_LINE[10:8] W 000* preset line: reference line

preset

A4h REFLINE_LSB 7 to 0 PRESET_LINE[7:0] W 01h*

A5h NPIX_MSB 7 to 5 x W 000* undeﬁned

4 to 0 NPIX[12:8] W 0 0000* number pixel: number of pixels

per line

A6h NPIX_LSB 7 to 0 NPIX[7:0] W 00h*

A7h NLINE_MSB 7 to 3 x W 0000 0* undeﬁned

2 to 0 NLINE[10:8] W 000* number line: number of lines

per frame

A8h NLINE_LSB 7 to 0 NLINE[7:0] W 00h*

TDA9983BHW/8/C1,51

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IC HDMI TX 81MHZ 80-HTQFP

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TDA9983BHW/8/C1,51

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