TDA9983BHW/8/C1,51 Datasheet TDA9983BHW/8/C1,55, TDA9983BHW/15/C1:5, TDA9983BHW/8/C1,51 | P55-P57

Product data sheet Rev. 01 — 20 May 2008 55 of 119

NXP Semiconductors

TDA9983B

150 MHz pixel rate HDMI transmitter

9.4.3 Current page address register

9.5 PLL settings page register deﬁnitions

The current page address for the PLL settings page is 02h.

The conﬁguration of the registers for this page is given in Table 66.

1 TOP_SEL W top select

0* top_tbg_sci = top_tbg_sci (internal;

programmed via I

C-bus)

1 top_tbg_sci = top_tbg_vrf

0 TOP_TGL W top toggle

0* no speciﬁc action

1 toggle top_tbg_sci

Table 64. TBG_CNTRL_0 register (address CAh) bit description

…continued

Legend: * = default value

Bit Symbol Access Value Description

Table 65. CURPAGE_ADR register (address FFh) bit description

Legend: * = default value

Bit Symbol Access Value Description

7 to 0 CURPAGE_ADR[7:0] W 00h* current page address: selects the current

memory page

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Product data sheet Rev. 01 — 20 May 2008 56 of 119

NXP Semiconductors

TDA9983B

150 MHz pixel rate HDMI transmitter

[1] R: reading register

W: writing register

x: bit must be set to default value for proper operation

-: not used

Table 66. I

C-bus registers of memory page 02h

[1]

addr

R/W Bit Default

value

7 (MSB) 6 5 4 3 2 1 0 (LSB)

PLL_SERIAL_1 00h R/W x SRL_MAN_IP SRL_REG_IP[2:0] SRL_IZ[1:0] SRL_FDN 0000 0000

PLL_SERIAL_2 01h R/W SRL_PR[3:0] x x SRL_NOSC[1:0] 0000 0000

PLL_SERIAL_3 02h R/W x x x SRL_PXIN_

SEL

x x SRL_DE SRL_CCIR 0000 0000

SERIALIZER 03h R/W SRL_PHASE3[3:0] SRL_PHASE2[3:0] 0000 0000

BUFFER_OUT 04h R/W x x x x SRL_FORCE[1:0] SRL_CLK[1:0] 0000 0000

PLL_SCG1 05h R/W x x x x x x x SCG_FDN 0000 0001

PLL_SCG2 06h R/W BYPASS_

SCG

x x SELPLLCL

KIN

x x SCG_NOSC[1:0] 1001 0000

PLL_SCGN1 07h R/W SCG_NDIV[7:0] 1111 1010

PLL_SCGN2 08h R/W x x x x x SCG_NDIV[10:8] 0000 0000

PLL_SCGR1 09h R/W SCG_RDIV[7:0] 0101 1011

PLL_SCGR2 0Ah R/W x x x x x x x SCG_

RDIV[8]

0000 0000

PLL_DE 0Bh R/W BYPASS_

PLLDE

x PLLDE_NOSC[1:0] x PLLDE_IZ[1:0] PLLDE_

FDN

1000 0001

CCIR_DIV 0Ch R/W x x x x x x x REFDIV2 0000 0001

VAI_PLL 0Dh R x PLLDE_HVP PLLSCG_

HVP

PLLSRL_

HVP

x PLLDE_

LOCK

PLLSCG_

LOCK

PLLSRL_

LOCK

0000 0000

AUDIO_DIV 0Eh R/W x x x x x AUDIO_DIV[2:0] 0000 0011

TEST1 0Fh R/W x x x TSTSER

PHOE

x x TST_NOSC TST_HVP 0000 0000

TEST2 10h R/W x x x x x x PWD1V8 DIVTESTOE 0000 0000

SEL_CLK 11h R/W x x x x ENA_SC_

CLK

SEL_VRF_CLK[1:0] SEL_CLK1 0000 0000

Not used 12h - - 0000 0000

::: : :

Not used FEh - - 0000 0000

CURPAGE_ADR FFh W CURPAGE_ADR[7:0] 0000 0000

Product data sheet Rev. 01 — 20 May 2008 57 of 119

NXP Semiconductors

TDA9983B

150 MHz pixel rate HDMI transmitter

9.5.1 PLL serial registers

Table 67. PLL_SERIAL_1 register (address 00h) bit description

Legend: * = default value

Bit Symbol Access Value Description

7 x R/W 0* undeﬁned

6 SRL_MAN_IP R/W serializer manual current pole

0* automatic setting of output current pole

charge pump (ip_auto)

1 manual setting of output current pole charge

pump (ip_manual)

5 to 3 SRL_REG_IP[2:0] R/W serializer current pole: PLL pole charge

pump output current (ip_manual)

000* 400 nA

001 200 nA

010 133 nA

011 100 nA

100 80 nA

101 66 nA

110 57 nA

111 50 nA

2 to 1 SRL_IZ[1:0] R/W serializer zero current: PLL zero charge

pump output current

00* Iz / 5

01 Iz / 10

10 Iz / 15

11 Iz / 20

0 SRL_FDN R/W serializer fdn

0* normal (PLL loop active)

1 standby (PLL loop open)

TDA9983BHW/8/C1,51

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IC HDMI TX 81MHZ 80-HTQFP

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TDA9983BHW/8/C1,51

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