TDA9983BHW/8/C1,51 Datasheet TDA9983BHW/8/C1,55, TDA9983BHW/15/C1:5, TDA9983BHW/8/C1,51 | P37-P39

Product data sheet Rev. 01 — 20 May 2008 37 of 119

NXP Semiconductors

TDA9983B

150 MHz pixel rate HDMI transmitter

Table 36. VS_LINE_STRT_xx, VS_PIX_STRT_xx, VS_LINE_END_xx, VS_PIX_END_xx registers (address A9h to

B8h) bit description

Legend: * = default value

Address Register Bit Symbol Access Value Description

A9h VS_LINE_STRT_1_MSB 7 to 3 x W 0000 0* undeﬁned

2 to 0 VS_LINE_START_1[10:8] W 000* vertical synchronization line

start 1: vertical synchronization

line number for start pulse in

ﬁeld 1

AAh VS_LINE_STRT_1_LSB 7 to 0 VS_LINE_START_1[7:0] W 00h*

ABh VS_PIX_STRT_1_MSB 7 to 5 x W 000* undeﬁned

4 to 0 VS_PIX_START_1[12:8] W 0 0000* vertical synchronization pixel

start 1: vertical synchronization

pixel number for start pulse in

ﬁeld 1

ACh VS_PIX_STRT_1_LSB 7 to 0 VS_PIX_START_1[7:0] W 00h*

ADh VS_LINE_END_1_MSB 7 to 3 x W 0000 0* undeﬁned

2 to 0 VS_LINE_END_1[10:8] W 000* vertical synchronization line

end 1: vertical synchronization

line number for end pulse in

ﬁeld 1

AEh VS_LINE_END_1_LSB 7 to 0 VS_LINE_END_1[7:0] W 00h*

AFh VS_PIX_END_1_MSB 7 to 5 x W 000* undeﬁned

4 to 0 VS_PIX_END_1[12:8] W 0 0000* vertical synchronization pixel

end 1: vertical synchronization

pixel number for end pulse in

ﬁeld 1

B0h VS_PIX_END_1_LSB 7 to 0 VS_PIX_END_1[7:0] W 00h*

B1h VS_LINE_STRT_2_MSB 7 to 3 x W 0000 0* undeﬁned

2 to 0 VS_LINE_START_2[10:8] W 000* vertical synchronization line

start 2: vertical synchronization

line number for start pulse in

ﬁeld 2

B2h VS_LINE_STRT_2_LSB 7 to 0 VS_LINE_START_2[7:0] W 00h*

B3h VS_PIX_STRT_2_MSB 7 to 5 x W 000* undeﬁned

4 to 0 VS_PIX_START_2[12:8] W 0 0000* vertical synchronization pixel

start 2: vertical synchronization

pixel number for start pulse in

ﬁeld 2

B4h VS_PIX_STRT_2_LSB 7 to 0 VS_PIX_START_2[7:0] W 00h*

B5h VS_LINE_END_2_MSB 7 to 3 x W 0000 0* undeﬁned

2 to 0 VS_LINE_END_2[10:8] W 000* vertical synchronization line

end 2: vertical synchronization

line number for end pulse in

ﬁeld 2

B6h VS_LINE_END_2_LSB 7 to 0 VS_LINE_END_2[7:0] W 00h*

B7h VS_PIX_END_2_MSB 7 to 5 x W 000* undeﬁned

4 to 0 VS_PIX_END_2[12:8] W 0 0000* vertical synchronization pixel

end 2: vertical synchronization

pixel number for end pulse in

ﬁeld 2

B8h VS_PIX_END_2_LSB 7 to 0 VS_PIX_END_2[7:0] W 00h*

Product data sheet Rev. 01 — 20 May 2008 38 of 119

NXP Semiconductors

TDA9983B

150 MHz pixel rate HDMI transmitter

Table 37. HS_PIX_xx registers (address B9h to BCh) bit description

Legend: * = default value

Address Register Bit Symbol Access Value Description

B9h HS_PIX_START_MSB 7 to 5 x W 000* undeﬁned

4 to 0 HS_PIX_START[12:8] W 0 0000* horizontal synchronization pixel

number for start pulse in ﬁeld 1

BAh HS_PIX_START_LSB 7 to 0 HS_PIX_START[7:0] W 00h*

BBh HS_PIX_STOP_MSB 7 to 5 x W 000* undeﬁned

4 to 0 HS_PIX_END[12:8] W 0 0000* horizontal synchronization pixel

number for end pulse in ﬁeld 2

BCh HS_PIX_STOP_LSB 7 to 0 HS_PIX_END[7:0] W 00h*

Table 38. VWIN_START_xx and VWIN_END_xx registers (address BDh and C4h) bit description

Legend: * = default value

Address Register Bit Symbol Access Value Description

BDh VWIN_START_1_MSB 7 to 3 x W 0000 0* undeﬁned

2 to 0 VWIN_START_1[10:8] W 000* vertical window start 1:

vertical window line number for

start pulse in ﬁeld 1

BEh VWIN_START_1_LSB 7 to 0 VWIN_START_1[7:0] W 00h*

BFh VWIN_END_1_MSB 7 to 3 x W 0000 0* undeﬁned

2 to 0 VWIN_END_1[10:8] W 000* vertical window end 1: vertical

window line number for end

pulse in ﬁeld 1

C0h VWIN_END_1_LSB 7 to 0 VWIN_END_1[7:0] W 00h*

C1h VWIN_START_2_MSB 7 to 3 x W 0000 0* undeﬁned

2 to 0 VWIN_START_2[10:8] W 000* vertical window start 2:

vertical window line number for

start pulse in ﬁeld 2

C2h VWIN_START_2_LSB 7 to 0 VWIN_START_2[7:0] W 00h*

C3h VWIN_END_2_MSB 7 to 3 x W 0000 0* undeﬁned

2 to 0 VWIN_END_2[10:8] W 000* vertical window end 2: vertical

window line number for end

pulse in ﬁeld 2

C4h VWIN_END_2_LSB 7 to 0 VWIN_END_2[7:0] W 00h*

Table 39. DE_xxx registers (address C5h to C8h) bit description

Legend: * = default value

Address Register Bit Symbol Access Value Description

C5h DE_START_MSB 7 to 5 x W 000* undeﬁned

4 to 0 DE_START[12:8] W 0 0000* data enable start: data enable

pixel number for start pulse in

ﬁeld 1

C6h DE_START_LSB 7 to 0 DE_START[7:0] W 00h*

C7h DE_STOP_MSB 7 to 5 x W 000* undeﬁned

4 to 0 DE_END[12:8] W 0 0000* data enable end: data enable

pixel number for end pulse in

ﬁeld 2

C8h DE_STOP_LSB 7 to 0 DE_END[7:0] W 00h*

Table 40. COLBAR_WIDTH register (address C9h) bit description

Legend: * = default value

Bit Symbol Access Value Description

7 to 0 CBW[7:0] W 00h* color bar width

Product data sheet Rev. 01 — 20 May 2008 39 of 119

NXP Semiconductors

TDA9983B

150 MHz pixel rate HDMI transmitter

Table 41. TBG_CNTRL_0 register (address CAh) bit description

Legend: * = default value

Bit Symbol Access Value Description

7 SYNC_ONCE W sync once

0* line/pixel counters are synchronized each

frame

1 line/pixel counters are synchronized only

once

6 SYNC_MTHD W sync method

0* synchronization is based on combination

of v and h

1 synchronization is based on combination

of v and x (de)

5 FRAME_DIS W frame disable: synchronized by linecnt = 1

AND pixelcnt = 1

0* enable video frames

1 disable video frames

4 to 0 x W 0 0000* undeﬁned

Table 42. TBG_CNTRL_1 register (address CBh) bit description

Legend: * = default value

Bit Symbol Access Value Description

7 x W 0* undeﬁned

6 DWIN_DIS W data island window disable

0* data island window active

1 data island window disabled

5 VHX_EXT[2] W vhx_ext 2: bit 2

0* vs = vs_tbg (internal)

1 vs = v_vip (external)

4 VHX_EXT[1] W vhx_ext 1: bit 1

0* hs = hs_tbg (internal)

1 hs = h_vip (external)

3 VHX_EXT[0] W vhx_ext 0: bit 0

0* de = de_tbg (internal)

1 de = x_vip (external)

2 VH_TGL[2] W vh_tgl 2: bit 2

0* vs/hs-polarity is determined by

vidformat_table

1 vs/hs-polarity depends on VH_TGL[1:0]

1 VH_TGL[1] W vh_tgl 1: bit 1

0* no speciﬁc action

1 toggle vs (only when VH_TGL[2] = 1)

0 VH_TGL[0] W vh_tgl 0: bit 0

0* no speciﬁc action

1 toggle hs (only when VH_TGL[2] = 1)

TDA9983BHW/8/C1,51

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Manufacturer:

NXP Semiconductors

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IC HDMI TX 81MHZ 80-HTQFP

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TDA9983BHW/8/C1,51

TDA9983BHW/8/C1,51

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