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TDA9983BHW/8/C1,51

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P72P73-P75P76-P78P79-P81P82-P84P85-P87P88-P90P91-P93P94-P96P97-P99P100-P102P103-P105P106-P108P109-P111P112-P114P115-P117P118-P119
TDA9983B_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 20 May 2008 91 of 119
NXP Semiconductors
TDA9983B
150 MHz pixel rate HDMI transmitter
9.7.2 ISRC packets registers
Below is an example of use. Please refer to
HDMI 1.2a specification
for the correct
definition of data bytes.
See
HDMI 1.2a specification, section 8.8
for rules regarding the use of the ISRC packets.
Table 101. CH_STAT_B_x channel status bytes 0, 1, 3 and 4 registers (address 14h to 17h) bit description
Legend: * = default value
Address Register Bit Symbol Access Value Description
channel status byte x:
x = 0 to 4
14h CH_STAT_B_0 7 to 0 CH_STAT_BYTE_0[7:0] R/W 00h* byte 0
15h CH_STAT_B_1 7 to 0 CH_STAT_BYTE_1[7:0] R/W 00h* byte 1
16h CH_STAT_B_3 7 to 0 CH_STAT_BYTE_3[7:0] R/W 00h* byte 3
17h CH_STAT_B_4 7 to 0 CH_STAT_BYTE_4[7:0] R/W 00h* byte 4
Table 102. CH_STAT_B_2_APx_n channel status byte 2 registers (address 18h to 1Fh) bit description
Legend: * = default value
Address Register Bit Symbol Access Value Description
channel status byte 2
of audio port x:
x = 0 to 3
18h CH_STAT_B_2_AP0_L 7 to 0 CH_STAT_BYTE_2_AP0_L[7:0] R/W 00h* audio port 0 left
19h CH_STAT_B_2_AP0_R 7 to 0 CH_STAT_BYTE_2_AP0_R[7:0] R/W 00h* audio port 0 right
1Ah CH_STAT_B_2_AP1_L 7 to 0 CH_STAT_BYTE_2_AP1_L[7:0] R/W 00h* audio port 1 left
1Bh CH_STAT_B_2_AP1_R 7 to 0 CH_STAT_BYTE_2_AP1_R[7:0] R/W 00h* audio port 1 right
1Ch CH_STAT_B_2_AP2_L 7 to 0 CH_STAT_BYTE_2_AP2_L[7:0] R/W 00h* audio port 2 left
1Dh CH_STAT_B_2_AP2_R 7 to 0 CH_STAT_BYTE_2_AP2_R[7:0] R/W 00h* audio port 2 right
1Eh CH_STAT_B_2_AP3_L 7 to 0 CH_STAT_BYTE_2_AP3_L[7:0] R/W 00h* audio port 3 left
1Fh CH_STAT_B_2_AP3_R 7 to 0 CH_STAT_BYTE_2_AP3_R[7:0] R/W 00h* audio port 3 right
Table 103. ISRC1 packet registers (address 20h to 3Eh) bit description
Legend: * = default value
Address Register Bit Symbol Access Value Description
20h ISRC1_PACKET_
TYPE
7 to 0 ISRC1_PACKET_TYPE[7:0] R/W 05h* ISRC1 packet type: packet type
of the ISRC1 packet
21h ISRC1_CTRL 7 ISRC_CONT R/W 0* ISRC continued: ISRC continued
in next packet
6 ISRC_VALID R/W 0* ISRC valid: ISRC status and data
are valid
5 to 3 ISRC1_RSVD[5:3] R/W 000* ISRC1 reserved: reserved (shall
be zero)
2 to 0 ISRC_STATUS[2:0] R/W 000* ISRC status
001 starting position
010 intermediate position
100 ending position
TDA9983B_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 20 May 2008 92 of 119
NXP Semiconductors
TDA9983B
150 MHz pixel rate HDMI transmitter
22h ISRC1_RSVD 7 to 0 ISRC1_RSVD[7:0] R/W 00h* ISRC1 reserved: reserved (shall
be zero)
ISRC1 data byte x: x = 0 to 15
23h UPC_EAN_ISRC_0 7 to 0 UPC_EAN_ISRC_0[7:0] R/W 00h* UPC/EAN or ISRC byte 0
24h UPC_EAN_ISRC_1 7 to 0 UPC_EAN_ISRC_1[7:0] R/W 00h* UPC/EAN or ISRC byte 1
25h UPC_EAN_ISRC_2 7 to 0 UPC_EAN_ISRC_2[7:0] R/W 00h* UPC/EAN or ISRC byte 2
26h UPC_EAN_ISRC_3 7 to 0 UPC_EAN_ISRC_3[7:0] R/W 00h* UPC/EAN or ISRC byte 3
27h UPC_EAN_ISRC_4 7 to 0 UPC_EAN_ISRC_4[7:0] R/W 00h* UPC/EAN or ISRC byte 4
28h UPC_EAN_ISRC_5 7 to 0 UPC_EAN_ISRC_5[7:0] R/W 00h* UPC/EAN or ISRC byte 5
29h UPC_EAN_ISRC_6 7 to 0 UPC_EAN_ISRC_6[7:0] R/W 00h* UPC/EAN or ISRC byte 6
2Ah UPC_EAN_ISRC_7 7 to 0 UPC_EAN_ISRC_7[7:0] R/W 00h* UPC/EAN or ISRC byte 7
2Bh UPC_EAN_ISRC_8 7 to 0 UPC_EAN_ISRC_8[7:0] R/W 00h* UPC/EAN or ISRC byte 8
2Ch UPC_EAN_ISRC_9 7 to 0 UPC_EAN_ISRC_9[7:0] R/W 00h* UPC/EAN or ISRC byte 9
2Dh UPC_EAN_ISRC_10 7 to 0 UPC_EAN_ISRC_10[7:0] R/W 00h* UPC/EAN or ISRC byte 10
2Eh UPC_EAN_ISRC_11 7 to 0 UPC_EAN_ISRC_11[7:0] R/W 00h* UPC/EAN or ISRC byte 11
2Fh UPC_EAN_ISRC_12 7 to 0 UPC_EAN_ISRC_12[7:0] R/W 00h* UPC/EAN or ISRC byte 12
30h UPC_EAN_ISRC_13 7 to 0 UPC_EAN_ISRC_13[7:0] R/W 00h* UPC/EAN or ISRC byte 13
31h UPC_EAN_ISRC_14 7 to 0 UPC_EAN_ISRC_14[7:0] R/W 00h* UPC/EAN or ISRC byte 14
32h UPC_EAN_ISRC_15 7 to 0 UPC_EAN_ISRC_15[7:0] R/W 00h* UPC/EAN or ISRC byte 15
ISRC1 data byte x: x = 16 to 27
33h ISRC1_PB16 7 to 0 ISRC1_PB_BYTE_16[7:0] R/W 00h* reserved byte 16 (shall be set to
a value of 0)
34h ISRC1_PB17 7 to 0 ISRC1_PB_BYTE_17[7:0] R/W 00h* reserved byte 17 (shall be set to
a value of 0)
35h ISRC1_PB18 7 to 0 ISRC1_PB_BYTE_18[7:0] R/W 00h* reserved byte 18 (shall be set to
a value of 0)
36h ISRC1_PB19 7 to 0 ISRC1_PB_BYTE_19[7:0] R/W 00h* reserved byte 19 (shall be set to
a value of 0)
37h ISRC1_PB20 7 to 0 ISRC1_PB_BYTE_20[7:0] R/W 00h* reserved byte 20 (shall be set to
a value of 0)
38h ISRC1_PB21 7 to 0 ISRC1_PB_BYTE_21[7:0] R/W 00h* reserved byte 21 (shall be set to
a value of 0)
39h ISRC1_PB22 7 to 0 ISRC1_PB_BYTE_22[7:0] R/W 00h* reserved byte 22 (shall be set to
a value of 0)
3Ah ISRC1_PB23 7 to 0 ISRC1_PB_BYTE_23[7:0] R/W 00h* reserved byte 23 (shall be set to
a value of 0)
3Bh ISRC1_PB24 7 to 0 ISRC1_PB_BYTE_24[7:0] R/W 00h* reserved byte 24 (shall be set to
a value of 0)
3Ch ISRC1_PB25 7 to 0 ISRC1_PB_BYTE_25[7:0] R/W 00h* reserved byte 25 (shall be set to
a value of 0)
3Dh ISRC1_PB26 7 to 0 ISRC1_PB_BYTE_26[7:0] R/W 00h* reserved byte 26 (shall be set to
a value of 0)
3Eh ISRC1_PB27 7 to 0 ISRC1_PB_BYTE_27[7:0] R/W 00h* reserved byte 27 (shall be set to
a value of 0)
Table 103. ISRC1 packet registers (address 20h to 3Eh) bit description
…continued
Legend: * = default value
Address Register Bit Symbol Access Value Description
TDA9983B_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 20 May 2008 93 of 119
NXP Semiconductors
TDA9983B
150 MHz pixel rate HDMI transmitter
Table 104. ISRC2 packet registers (address 40h to 5Eh) bit description
Legend: * = default value
Address Register Bit Symbol Access Value Description
40h ISRC2_PACKET_
TYPE
7 to 0 ISRC2_PACKET_TYPE[7:0] R/W 06h* ISRC2 packet type: packet type
of the ISRC2 packet
41h ISRC2_RSVD1 7 to 0 ISRC2_RSVD1[7:0] R/W 00h* ISRC2 reserved 1: reserved
(shall be zero)
42h ISRC2_RSVD2 7 to 0 ISRC2_RSVD2[7:0] R/W 00h* ISRC2 reserved 2: reserved
(shall be zero)
ISRC2 data byte x: x = 0 to 15
43h UPC_EAN_ISRC_16 7 to 0 UPC_EAN_ISRC_16[7:0] R/W 00h* UPC/EAN or ISRC byte 16
44h UPC_EAN_ISRC_17 7 to 0 UPC_EAN_ISRC_17[7:0] R/W 00h* UPC/EAN or ISRC byte 17
45h UPC_EAN_ISRC_18 7 to 0 UPC_EAN_ISRC_18[7:0] R/W 00h* UPC/EAN or ISRC byte 18
46h UPC_EAN_ISRC_19 7 to 0 UPC_EAN_ISRC_19[7:0] R/W 00h* UPC/EAN or ISRC byte 19
47h UPC_EAN_ISRC_20 7 to 0 UPC_EAN_ISRC_20[7:0] R/W 00h* UPC/EAN or ISRC byte 20
48h UPC_EAN_ISRC_21 7 to 0 UPC_EAN_ISRC_21[7:0] R/W 00h* UPC/EAN or ISRC byte 21
49h UPC_EAN_ISRC_22 7 to 0 UPC_EAN_ISRC_22[7:0] R/W 00h* UPC/EAN or ISRC byte 22
4Ah UPC_EAN_ISRC_23 7 to 0 UPC_EAN_ISRC_23[7:0] R/W 00h* UPC/EAN or ISRC byte 23
4Bh UPC_EAN_ISRC_24 7 to 0 UPC_EAN_ISRC_24[7:0] R/W 00h* UPC/EAN or ISRC byte 24
4Ch UPC_EAN_ISRC_25 7 to 0 UPC_EAN_ISRC_25[7:0] R/W 00h* UPC/EAN or ISRC byte 25
4Dh UPC_EAN_ISRC_26 7 to 0 UPC_EAN_ISRC_26[7:0] R/W 00h* UPC/EAN or ISRC byte 26
4Eh UPC_EAN_ISRC_27 7 to 0 UPC_EAN_ISRC_27[7:0] R/W 00h* UPC/EAN or ISRC byte 27
4Fh UPC_EAN_ISRC_28 7 to 0 UPC_EAN_ISRC_28[7:0] R/W 00h* UPC/EAN or ISRC byte 28
50h UPC_EAN_ISRC_29 7 to 0 UPC_EAN_ISRC_29[7:0] R/W 00h* UPC/EAN or ISRC byte 29
51h UPC_EAN_ISRC_30 7 to 0 UPC_EAN_ISRC_30[7:0] R/W 00h* UPC/EAN or ISRC byte 30
52h UPC_EAN_ISRC_31 7 to 0 UPC_EAN_ISRC_31[7:0] R/W 00h* UPC/EAN or ISRC byte 31
ISRC2 data byte x: x = 16 to 27
53h ISRC2_PB16 7 to 0 ISRC2_PB_BYTE_16[7:0] R/W 00h* reserved byte 16 (shall be set to
a value of 0)
54h ISRC2_PB17 7 to 0 ISRC2_PB_BYTE_17[7:0] R/W 00h* reserved byte 17 (shall be set to
a value of 0)
55h ISRC2_PB18 7 to 0 ISRC2_PB_BYTE_18[7:0] R/W 00h* reserved byte 18 (shall be set to
a value of 0)
56h ISRC2_PB19 7 to 0 ISRC2_PB_BYTE_19[7:0] R/W 00h* reserved byte 19 (shall be set to
a value of 0)
57h ISRC2_PB20 7 to 0 ISRC2_PB_BYTE_20[7:0] R/W 00h* reserved byte 20 (shall be set to
a value of 0)
58h ISRC2_PB21 7 to 0 ISRC2_PB_BYTE_21[7:0] R/W 00h* reserved byte 21 (shall be set to
a value of 0)
59h ISRC2_PB22 7 to 0 ISRC2_PB_BYTE_22[7:0] R/W 00h* reserved byte 22 (shall be set to
a value of 0)
5Ah ISRC2_PB23 7 to 0 ISRC2_PB_BYTE_23[7:0] R/W 00h* reserved byte 23 (shall be set to
a value of 0)
5Bh ISRC2_PB24 7 to 0 ISRC2_PB_BYTE_24[7:0] R/W 00h* reserved byte 24 (shall be set to
a value of 0)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P72P73-P75P76-P78P79-P81P82-P84P85-P87P88-P90P91-P93P94-P96P97-P99P100-P102P103-P105P106-P108P109-P111P112-P114P115-P117P118-P119

TDA9983BHW/8/C1,51

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Manufacturer:
NXP Semiconductors
Description:
IC HDMI TX 81MHZ 80-HTQFP
Lifecycle:
New from this manufacturer.
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