72V3640L6BB Datasheet 72V3670L10PFG, 72V3690L7-5PFGI, 72V3660L6PFG | P13-P15

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC II

36-BIT FIFO

1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36

PROGRAMMING FLAG OFFSETS

Full and Empty Flag offset values are user programmable. The IDT72V3640/

72V3650/72V3660/72V3670/72V3680/72V3690 have internal registers for

these offsets. There are eight default offset values selectable during Master

Reset. These offset values are shown in Table 2. Offset values can also be

programmed into the FIFO in one of two ways; serial or parallel loading method.

The selection of the loading method is done using the LD (Load) pin. During

Master Reset, the state of the LD input determines whether serial or parallel flag

offset programming is enabled. A HIGH on LD during Master Reset selects serial

loading of offset values. A LOW on LD during Master Reset selects parallel

loading of offset values.

In addition to loading offset values into the FIFO, it is also possible to read

the current offset values. Offset values can be read via the parallel output port

Q0-Qn, regardless of the programming mode selected (serial or parallel). It is

not possible to read the offset values in serial fashion.

Figure 3, Programmable Flag Offset Programming Sequence, summaries

the control pins and sequence for both serial and parallel programming modes.

For a more detailed description, see discussion that follows.

The offset registers may be programmed (and reprogrammed) any time after

Master Reset, regardless of whether serial or parallel programming has been

selected. Valid programming ranges are from 0 to D-1.

SYNCHRONOUS vs ASYNCHRONOUS PROGRAMMABLE FLAG

TIMING SELECTION

The IDT72V3640/72V3650/72V3660/72V3670/72V3680/72V3690 can

be configured during the Master Reset cycle with either synchronous or

asynchronous timing for PAF and PAE flags by use of the PFM pin.

If synchronous PAF/PAE configuration is selected (PFM, HIGH during

MRS), the PAF is asserted and updated on the rising edge of WCLK only and

not RCLK. Similarly, PAE is asserted and updated on the rising edge of RCLK

only and not WCLK. For detail timing diagrams, see Figure 17 for synchronous

PAF timing and Figure 18 for synchronous PAE timing.

If asynchronous PAF/PAE configuration is selected (PFM, LOW during

MRS), the PAF is asserted LOW on the LOW-to-HIGH transition of WCLK and

PAF is reset to HIGH on the LOW-to-HIGH transition of RCLK. Similarly, PAE

is asserted LOW on the LOW-to-HIGH transition of RCLK. PAE is reset to HIGH

on the LOW-to-HIGH transition of WCLK. For detail timing diagrams, see Figure

19 for asynchronous PAF timing and Figure 20 for asynchronous PAE timing.

IDT72V3640, 72V3650

LD FSEL1 FSEL0 Offsets n,m

LH L511

L L H 255

L L L 127

LH H63

HL L31

HH L15

HL H7

HH H3

LD FSEL1 FSEL0 Program Mode

H X X Serial

(3)

L X X Parallel

(4)

IDT72V3660, 72V3670, 72V3680, 72V3690

LD FSEL1 FSEL0 Offsets n,m

H L L 1,023

LH L511

L L H 255

L L L 127

LH H63

HH L31

HL H15

HH H7

LD FSEL1 FSEL0 Program Mode

H X X Serial

(3)

L X X Parallel

(4)

TABLE 2 — DEFAULT PROGRAMMABLE

FLAG OFFSETS

NOTES:

1. n = empty offset for PAE.

2. m = full offset for PAF.

3. As well as selecting serial programming mode, one of the default values will also

be loaded depending on the state of FSEL0 & FSEL1.

4. As well as selecting parallel programming mode, one of the default values will

also be loaded depending on the state of FSEL0 & FSEL1.

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC II

36-BIT FIFO

1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36

(n+2) to 4,097

4,098 to (8,193(m+1))

8,193

IDT72V3670

4667 drw05

(n+2) to 8,193 (n+2) to 16,385

8,194 to (16,385-(m+1))

16,386 to (32,769-(m+1))

16,385 32,769

IDT72V3680

IDT72V3690

IR PAF

PAE OR

HLH

LHL HL

LHL

Number of

Words in

FIFO

TABLE 4 ⎯ STATUS FLAGS FOR FWFT MODE

TABLE 3 ⎯ STATUS FLAGS FOR IDT STANDARD MODE

FF PAF

PAE EF

HHLH H

LHH

1 to n

(1)

(n+1) to 512

513 to (1,024-(m+1))

(1,024-m) to 1,023

1,024

IDT72V3640

(n+1) to 1,024 (n+1) to 2,048

1,025 to (2,048-(m+1))

2,049 to (4,096-(m+1))

(2,048-m) to 2,047 (4,096m) to 4,095

2,048 4,096

IDT72V3650

IDT72V3660

FF PAF

PAE EF

HHLH H

LHH

(n+1) to 4,096

4,097 to (8,192-(m+1))

(8,192-m) to 8,191

8,192

IDT72V3670

(n+1) to 8,192 (n+1) to 16,384

8,193 to (16,384-(m+1))

16,385 to (32,768-(m+1))

(16,384-m)

to 16,383

(32,768-m)

to 32,767

16,384 32,768

IDT72V3680

IDT72V3690

Number of

Words in

FIFO

1 to n

(1)

1 to n

(1)

1 to n

(1)

1 to n

(1)

1 to n

(1)

Number of

Words in

FIFO

1 to n+1

(n+2) to 513

514 to (1,025-(m+1))

(1,025-m) to 1,024

1,025

IDT72V3640

(n+2) to 1,025 (n+2) to 2,049

1,026 to (2,049-(m+1))

2,050 to (4,097-(m+1))

(2,049-m) to 2,048 (4,097m) to 4,096

2,049 4,097

IDT72V3650

IDT72V3660

Number of

Words in

FIFO

IR PAF

PAE OR

HLH

LHL HL

LHL

1 to n+1 1 to n+1

1 to n+1 1 to n+1 1 to n+1

(8,194-m) to 8,192

(16,385-m) to 16,384 (32,769-m) to 32,768

NOTE:

1. See table 2 for values for n, m.

NOTE:

1. See table 2 for values for n, m.

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC II

36-BIT FIFO

1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36

Figure 3. Programmable Flag Offset Programming Sequence

NOTES:

1. The programming method can only be selected at Master Reset.

2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.

3. The programming sequence applies to both IDT Standard and FWFT modes.

WCLK RCLK

WEN

REN

SEN

No Operation

Write Memory

Read Memory

No Operation

Parallel write to registers:

Empty Offset (LSB)

Empty Offset (MSB)

Full Offset (LSB)

Full Offset (MSB)

IDT72V3640

IDT72V3650

IDT72V3660

IDT72V3670

IDT72V3680

IDT72V3690

Parallel read from registers:

Empty Offset (LSB)

Empty Offset (MSB)

Full Offset (LSB)

Full Offset (MSB)

Serial shift into registers:

20 bits for the 72V3640

22 bits for the 72V3650

24 bits for the 72V3660

26 bits for the 72V3670

28 bits for the 72V3680

30 bits for the 72V3690

1 bit for each rising WCLK edge

Starting with Empty Offset (LSB)

Ending with Full Offset (MSB)

4667 drw06

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P45 P46-P46

72V3640L6BB

Mfr. #:

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Description:

FIFO 3.3V 32K X 36 SSII

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72V3640L6BB

72V3640L6BB

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