1SX250LH3F55I2LG Datasheet 1SX280LH3F55E2VG, 1SX280LH2F55E2VG, 1SX250LH2F55E1VG | P19-P21

Figure 7. Intel Stratix 10 Receiver Block Features

∑

VGA CDR

DFE Eye Viewer

CTLE

Adaptive Parametric Tuning Engine

Deserializer

All link equalization parameters feature automatic adaptation using the new Advanced

Digital Adaptive Parametric Tuning (ADAPT) circuit. This circuit is used to dynamically

set DFE tap weights, adjust CTLE parameters, and optimize VGA gain and threshold

voltage. Finally, optimal and consistent signal integrity is ensured by using the new

hardened Precision Signal Integrity Calibration Engine (PreSICE) to automatically

calibrate all transceiver circuit blocks on power-up. This gives the most link margin

and ensures robust, reliable, and error-free operation.

Table 8. Transceiver PMA Features

Feature Capability

Chip-to-Chip Data Rates 1 Gbps

(8)

to 28.3 Gbps (Intel Stratix 10 GX/SX devices)

Backplane Support Drive backplanes at data rates up to 28.3 Gbps, including 10GBASE-KR compliance

Optical Module Support SFP+/SFP, XFP, CXP, QSFP/QSFP28, QSFPDD, CFP/CFP2/CFP4

Cable Driving Support SFP+ Direct Attach, PCI Express over cable, eSATA

Transmit Pre-Emphasis 5-tap transmit pre-emphasis and de-emphasis to compensate for system channel loss

Continuous Time Linear

Equalizer (CTLE)

Dual mode, high-gain, and high-data rate, linear receive equalization to compensate for

system channel loss

Decision Feedback Equalizer

(DFE)

15 fixed tap DFE to equalize backplane channel loss in the presence of crosstalk and noisy

environments

Advanced Digital Adaptive

Parametric Tuning (ADAPT)

Fully digital adaptation engine to automatically adjust all link equalization parameters—

including CTLE, DFE, and VGA blocks—that provide optimal link margin without intervention

from user logic

Precision Signal Integrity

Calibration Engine (PreSICE)

Hardened calibration controller to quickly calibrate all transceiver control parameters on

power-up, which provides the optimal signal integrity and jitter performance

ATX Transmit PLLs Low jitter ATX (inductor-capacitor) transmit PLLs with continuous tuning range to cover a

wide range of standard and proprietary protocols, with optional fractional frequency

synthesis capability

Fractional PLLs On-chip fractional frequency synthesizers to replace on-board crystal oscillators and reduce

system cost

continued...

(8)

Stratix 10 transceivers can support data rates below 1 Gbps with over sampling.

1. Intel

Stratix

10 GX/SX Device Overview

S10-OVERVIEW | 2018.08.08

Stratix 10 GX/SX Device Overview

Feature Capability

Digitally Assisted Analog

CDR

Superior jitter tolerance with fast lock time

On-Die Instrumentation—

Eye Viewer and Jitter Margin

Tool

Simplify board bring-up, debug, and diagnostics with non-intrusive, high-resolution eye

monitoring (Eye Viewer). Also inject jitter from transmitter to test link margin in system.

Dynamic Reconfiguration Allows for independent control of each transceiver channel Avalon memory-mapped

interface for the most transceiver flexibility.

Multiple PCS-PMA and PCS-

Core to FPGA fabric interface

widths

8-, 10-, 16-, 20-, 32-, 40-, or 64-bit interface widths for flexibility of deserialization width,

encoding, and reduced latency

1.8.2. PCS Features

Intel Stratix 10 PMA channels interface with core logic through configurable and

bypassable PCS interface layers.

The PCS contains multiple gearbox implementations to decouple the PMA and PCS

interface widths. This feature provides the flexibility to implement a wide range of

applications with 8, 10, 16, 20, 32, 40, or 64-bit interface width between each

transceiver and the core logic.

The PCS also contains hard IP to support a variety of standard and proprietary

protocols across a wide range of data rates and encoding schemes. The Standard PCS

mode provides support for 8B/10B encoded applications up to 12.5 Gbps. The

Enhanced PCS mode supports 64B/66B and 64B/67B encoded applications up to 17.4

Gbps. The enhanced PCS mode also includes an integrated 10GBASE-KR/40GBASE-

KR4 Forward Error Correction (FEC) circuit. For highly customized implementations, a

PCS Direct mode provides an interface up to 64 bits wide to allow for custom encoding

and support for data rates up to 28.3 Gbps.

For more information about the PCS-Core interface or the double rate transfer mode,

refer to the Intel Stratix 10 L- and H-Tile Transceiver PHY User Guide, and the Intel

Stratix 10 E-Tile Transceiver PHY User Guide.

Table 9. Transceiver PCS Features

PCS Protocol

Support

Data Rate (Gbps) Transmitter Data Path Receiver Data Path

Standard PCS 1 to 12.5 Phase compensation FIFO, byte

serializer, 8B/10B encoder, bit-slipper,

channel bonding

Rate match FIFO, word-aligner, 8B/10B

decoder, byte deserializer, byte

ordering

PCI Express

Gen1/Gen2 x1,

x2, x4, x8, x16

2.5 and 5.0 Same as Standard PCS plus PIPE 2.0

interface to core

Same as Standard PCS plus PIPE 2.0

interface to core

PCI Express Gen3

x1, x2, x4, x8,

x16

8.0 Phase compensation FIFO, byte

serializer, encoder, scrambler, bit-

slipper, gear box, channel bonding, and

PIPE 3.0 interface to core, auto speed

negotiation

Rate match FIFO (0-600 ppm mode),

word-aligner, decoder, descrambler,

phase compensation FIFO, block sync,

byte deserializer, byte ordering, PIPE

3.0 interface to core, auto speed

negotiation

CPRI 0.6144 to 9.8 Same as Standard PCS plus

deterministic latency serialization

Same as Standard PCS plus

deterministic latency deserialization

continued...

1. Intel

Stratix

10 GX/SX Device Overview

S10-OVERVIEW | 2018.08.08

Stratix 10 GX/SX Device Overview

PCS Protocol

Support

Data Rate (Gbps) Transmitter Data Path Receiver Data Path

Enhanced PCS 2.5 to 17.4 FIFO, channel bonding, bit-slipper, and

gear box

FIFO, block sync, bit-slipper, and gear

box

10GBASE-R 10.3125 FIFO, 64B/66B encoder, scrambler,

FEC, and gear box

FIFO, 64B/66B decoder, descrambler,

block sync, FEC, and gear box

Interlaken 4.9 to 17.4 FIFO, channel bonding, frame

generator, CRC-32 generator,

scrambler, disparity generator, bit-

slipper, and gear box

FIFO, CRC-32 checker, frame sync,

descrambler, disparity checker, block

sync, and gear box

SFI-S/SFI-5.2 11.3 FIFO, channel bonding, bit-slipper, and

gear box

FIFO, bit-slipper, and gear box

IEEE 1588 1.25 to 10.3125 FIFO (fixed latency), 64B/66B encoder,

scrambler, and gear box

FIFO (fixed latency), 64B/66B decoder,

descrambler, block sync, and gear box

SDI up to 12.5 FIFO and gear box FIFO, bit-slipper, and gear box

GigE 1.25 Same as Standard PCS plus GigE state

machine

Same as Standard PCS plus GigE state

machine

PCS Direct up to 28.3 Custom Custom

Related Information

Intel Stratix 10 L- and H-Tile Transceiver PHY User Guide

1.9. PCI Express Gen1/Gen2/Gen3 Hard IP

Intel Stratix 10 devices contain embedded PCI Express hard IP designed for

performance, ease-of-use, increased functionality, and designer productivity.

The PCI Express hard IP consists of the PHY, Data Link, and Transaction layers. It also

supports PCI Express Gen1/Gen2/Gen3 end point and root port, in x1/x2/x4/x8/x16

lane configurations. The PCI Express hard IP is capable of operating independently

from the core logic (autonomous mode). This feature allows the PCI Express link to

power up and complete link training in less than 100 ms, while the rest of the device

is still in the process of being configured. The hard IP also provides added

functionality, which makes it easier to support emerging features such as Single Root

I/O Virtualization (SR-IOV) and optional protocol extensions.

The PCI Express hard IP has improved end-to-end data path protection using Error

Checking and Correction (ECC). In addition, the hard IP supports configuration of the

device via protocol (CvP) across the PCI Express bus at Gen1/Gen2/Gen3 rates.

1.10. Interlaken PCS Hard IP

Intel Stratix 10 devices have integrated Interlaken PCS hard IP supporting rates up to

17.4 Gbps per lane.

The Interlaken PCS hard IP is based on the proven functionality of the PCS developed

for Intel’s previous generation FPGAs, which has demonstrated interoperability with

Interlaken ASSP vendors and third-party IP suppliers. The Interlaken PCS hard IP is

present in every transceiver channel in Intel Stratix 10 devices.

1. Intel

Stratix

10 GX/SX Device Overview

S10-OVERVIEW | 2018.08.08

Stratix 10 GX/SX Device Overview

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