powered up and active within the 100 ms time allowed by the PCI Express
specification. Intel Stratix 10 devices also support partial reconfiguration across the
PCI Express bus which reduces system down time by keeping the PCI Express link
active while the device is being reconfigured.
1.23. Partial and Dynamic Reconfiguration
Partial reconfiguration allows you to reconfigure part of the FPGA while other sections
continue running. This capability is required in systems where uptime is critical,
because it allows you to make updates or adjust functionality without disrupting
services.
In addition to lowering power and cost, partial reconfiguration also increases the
effective logic density by removing the necessity to place in the FPGA those functions
that do not operate simultaneously. Instead, these functions can be stored in external
memory and loaded as needed. This reduces the size of the required FPGA by allowing
multiple applications on a single FPGA, saving board space and reducing power. The
partial reconfiguration process is built on top of the proven incremental compile design
flow in the Intel Quartus Prime design software
Dynamic reconfiguration in Intel Stratix 10 devices allows transceiver data rates,
protocols and analog settings to be changed dynamically on a channel-by-channel
basis while maintaining data transfer on adjacent transceiver channels. Dynamic
reconfiguration is ideal for applications that require on-the-fly multiprotocol or multi-
rate support. Both the PMA and PCS blocks within the transceiver can be reconfigured
using this technique. Dynamic reconfiguration of the transceivers can be used in
conjunction with partial reconfiguration of the FPGA to enable partial reconfiguration of
both core and transceivers simultaneously.
1.24. Fast Forward Compile
The innovative Fast Forward Compile feature in the Intel Quartus Prime software
identifies performance bottlenecks in your design and provides detailed, step-by-step
performance improvement recommendations that you can then implement. The
Compiler reports estimates of the maximum operating frequency that can be achieved
by applying the recommendations. As part of the new Hyper-Aware design flow, Fast
Forward Compile maximizes the performance of your Intel Stratix 10 design and
achieves rapid timing closure.
Previously, this type of optimization required multiple time-consuming design
iterations, including full design re-compilation to determine the effectiveness of the
changes. Fast Forward Compile enables you to make better decisions about where to
focus your optimization efforts, and how to increase your design performance and
throughput. This technique removes much of the guesswork of performance
exploration, resulting in fewer design iterations and as much as 2X core performance
gains for Intel Stratix 10 designs.
1.25. Single Event Upset (SEU) Error Detection and Correction
Intel Stratix 10 FPGAs and SoCs offer robust SEU error detection and correction
circuitry. The detection and correction circuitry includes protection for Configuration
RAM (CRAM) programming bits and user memories. The CRAM is protected by a
continuously running parity checker circuit with integrated ECC that automatically
corrects one or two bit errors and detects higher order multibit errors.
1. Intel
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Stratix
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10 GX/SX Device Overview
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Stratix 10 GX/SX Device Overview
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