22
INDUSTRIAL TEMPERATURE RANGE
IDT5V9885T
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
PROGRAMMING THE DEVICE
I
2
C and JTAG may be used to program the 5V9885T. The I
2
C/JTAG pin selects the I
2
C when HIGH and JTAG when LOW. Note that the TRST pin needs
to be LOW for I
2
C mode.
Hardwired Parameters for the IDT5V9885T
JTAG identification number = 32'b0000_0000001110101100_00000110011_1
Device (slave) address = 7'b1101010
ID Byte for the 5V9885T = 8'b00010000
I
2
C PROGRAMMING
The 5V9885T is programmed through an I
2
C-Bus serial interface, and is an I
2
C slave device. The read and write transfer formats are supported. The first
byte of data after a write frame to the correct slave address is interpreted as the register address; this address auto-increments after each byte written or read.
The frame formats are shown below.
SDA
SCL
S
Start
Condition
Data Frame
Data is stable during
clock HIGH
Stop
Condition
P
SCL
SDA
MSB LSB
R/W
7-bit slave address
R/W
0 - Slave will be written by master
1 - Slave will be read by master
The first byte transmitted by the Master is the Slave Address followed by the R/W bit.
The Slave acknowledges by sending a "1" bit.
ACK from Slave
1101010
Figure 1: Framing
Figure 2: First Byte Transmittetd on I
2
C Bus
Each frame starts with a "Start Condition" and ends with an "End Condition". These are both generated by the Master device.
23
INDUSTRIAL TEMPERATURE RANGE
IDT5V9885T
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
EXTERNAL I
2
C INTERFACE CONDITION
PROGWRITE
Writes can continue as long as a Stop condition is not sent and each byte will increment the register address.
PROGREAD
S Address R/W ACK Command Code Register Data PACKACK ACK
7-bits 0 1-bit 8-bits: xxxxxx00 1-bit 8-bits
1-bit 8-bits 1-bit
S Address R/W ACK Command Code Register PACKACK
7-bits 0 1-bit 8-bits: xxxxxx00 1-bit 8-bits
1-bit
ACK
8-bits
Data_1
1-bit
Sr Address R/W ACK ID Byte NACK
7-bits 1 1-bit 8 bits
1-bit
P
ACK
8-bits
Data_2
1-bit
ACK
8-bits
Data_last
1-bit
Figure 3: Progwrite Command Frame
Note: If the expected read command is not from the next higher register to the previous read or write command, then set a known "read" register address
prior to a read operation by issuing the following command:
KEY:
From Master to Slave
From Master to Slave, but can be omitted if followed by the correct sequence
Normally data transfer is terminated by a STOP condition generated by the Master. However, if the Master still wishes to communicate on the bus, it can
generate a repeated START condition, and address another Slave address without first generating a STOP condition.
From Slave to Master
SYMBOLS:
ACK - Acknowledge (SDA LOW)
NACK - Not Acknowledge (SDA HIGH)
Sr - Repeated Start Condition
S - START Condition
P - STOP Condition
The user can ignore the STOP condition above and use a repeated START condition instead, straight after the slave acknowledgement bit (i.e., followed by
the Progread command):
Note: Figure 4b above by itself is the Progread command format. The ID byte for the 5V9885T is 10hex. Each byte recieved increments the register address.
Figure 4a: Prior to Progread Command Set Register Address
Figure 4b: Progread Command Frame
24
INDUSTRIAL TEMPERATURE RANGE
IDT5V9885T
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
EEPROM INTERFACE
The IDT5V9885T can also store its configuration in an internal EEPROM. The contents of the device's internal programming registers can be saved to the
EEPROM by issuing a save instruction (ProgSave) and can be loaded back to the internal programming registers by issuing a restore instruction (ProgRestore).
To initiate a save or restore using I
2
C, only two bytes are transferred. The Device Address is issued with the read/write bit set to "0", followed by the appropriate
command code. The save or restore instruction executes after the STOP condition is issued by the Master, during which time the IDT5V9885T will not generate
Acknowledge bits. The IDT5V9885T will acknowledge the instructions after it has completed execution of them. During that time, the I
2
C bus should be interpreted
as busy by all other users of the bus.
Using JTAG, the ProgSave and ProgRestore instructions selects the BYPASS register path for shifting the data from TDI to TDO during the data register scanning.
During the execution of a ProgSave or ProgRestore instruction, the IDT5V9885T will not accept a new programming instruction (read, write, save, or restore).
All non-programming JTAG instructions will function properly, but the user should wait until the save or restore is complete before issuing a new programming
instruction. If a new programming instruction is issued before the save or restore completes, the new instruction is ignored, and the BYPASS register path remains
in effect for shifting data from TDI to TDO during data register scanning.
The time it takes for the save (TSAVE) and restore (TRESTORE) instructions to complete is:
TSAVE = 100ms max, TRESTORE = 10 ms max
PROGSAVE
PROGRESTORE
NOTE:
PROGWRITE is for writing to the 5V9885T registers.
PROGREAD is for reading the 5V9885T registers.
PROGSAVE is for saving all the contents of the 5V9885T registers to the EEPROM.
PROGRESTORE is for loading the entire EEPROM contents to the 5V9885T registers.
S Address R/W ACK Command Code ACK
7-bits 0 1-bit 8-bits:xxxxxx01
1-bit
P
S Address R/W ACK Command Code ACK
7-bits 0 1-bit 8-bits:xxxxxx10
1-bit
P
JTAG INTERFACE
In addition to the IEEE 1149.1 instructions EXTEST, SAMPLE/PRELOAD,
CLAMP, HIGH-Z and BYPASS, the 5V9885T allows access to internal
programming registers using the REGADDR (set register address), REGDATAR
(read register) and REGDATW (write register instructions. Data is always
accessed by byte, and the register address increments after each read or write.
The full instruction set follows. The IDT5V9885T will be updating the registers
during programming.
The JTAG TAP controller can be reset in one of four ways:
1) Power up in JTAG mode
2) Power up in I
2
C mode and then go into JTAG mode, or go out of and back
into JTAG mode with the I
2
C/JTAG pin
3) Apply TRST while in JTAG mode
4) Apply five rising edges of TCK with TMS high while in JTAG mode
IR (3) IR (2) IR (1) IR (0) Instructions
0 0 0 0 EXTEST
(1)
0 0 0 1 SAMPLE/PRELOAD
(1)
0 0 1 0 IDCODE
(1)
0 0 1 1 REGADDR
(2)
0 1 0 0 REGDATAW / PROGWRITE
(3)
0 1 0 1 REGDATAR / PROGREAD
(4)
0 1 1 0 PROGSAVE
(5)
0 1 1 1 PROGRESTORE
(6)
1 0 0 0 CLAMP
(1)
1 0 0 1 HIGHZ
(1,7)
1 1 1 1 BYPASS
(1)
JTAG INSTRUCTION REGISTER
DESCRIPTION
NOTES:
1. IEEE 1149.1 definition
2. REGADDR is for setting a specific 5V9885T register address.
3. REGDATAW/PROGWRITE is for writing to the 5V9885T registers.
4. REGDATAR/PROGREAD is for reading the 5V9885T registers.
5. PROGSAVE is for saving all the contents of the 5V9885T registers to the EEPROM.
6. PROGRESTORE is for loading the entire EEPROM contents to the 5V9885T registers.
7. The OEMs bits for OUT1-6 must be set for tri-state when using the HIGHZ instruction

5V9885TPFGI8

Mfr. #:
Manufacturer:
IDT
Description:
Clock Generators & Support Products SPREAD SPECTRUM PROG . CLK
Lifecycle:
New from this manufacturer.
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