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INDUSTRIAL TEMPERATURE RANGE
IDT5V9885T
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
Feedback-Divider
N[11:0] and A[3:0] are the bits used to program the feedback-divider for PLL0 (N0 and A0) and PLL1 (N1 and A1). If spread spectrum generation is enabled
for either PLL0 or PLL1, then the SS_OFFSET[5:0] bits (0x61, 0x69) would be factored into the overall feedback divider value. See the SPREAD SPECTRUM
GENERATION section for more details on how to configure PLL0 and PLL1 when spread spectrum is enabled. The two PLLs can also be configured for fractional
divide ratios. See FRACTIONAL DIVIDER for more details. For PLL2, only the N[11:0] bits (N2) are used to program its feedback divider and there is no spread
spectrum generation and fractional divides capability. The12-bit feedback-divider integer values range from 1 to 4095.
The following equations govern how the feedback divider value is set. Note that the equations are different for PLL0/PLL1 and PLL2
PLL0 and PLL1:
M = 2*N[11:0] + A[3:0] + 1 + SS_OFFSET[5:0] * 1/64 (Eq. 3)
M = 2*N[11:0] + A[3:0] + 1 (spread spectrum disabled) (Eq. 4)
A[3:0] = 0000 = -1
= 0001 = 1
= 0010 = 2
= 0011 = 3
.
.
.
= 1111 = 15
Note: A[3:0] < (N[11:0] - 5), must be met when using A. N cannot be programmed with a value of 4, 8, or 16 when using A.
PLL2:
M = N[11:0] (Eq. 5)
The user can achieve an even or odd integer divide ratio for both PLL0 and PLL1 by setting the A[3:0] bits accordingly and disabling the spread spectrum.
A fractional divide can also be set for PLL0 and PLL1 by using the A[3:0] bits in conjunction with the SS_OFFSET[5:0] bits, which is detailed in the FRACTIONAL
DIVIDER section. Note that the VCO has a frequency range of 10MHz to 1200MHz. To maintain low jitter, it is best to maximize the VCO frequency. For example,
if the reference clock is 100MHz and a 200MHz clock is required, to achieve the best jitter performance, multiply the 100MHz by 12 to get the VCO running at
the highest possible frequency of 1200MHz and then divide it down to get 200MHz. Or if the reference clock is 25MHz and 20MHz is the required clock, multiply
the 25MHz by 40 to get the VCO running at 1000MHz and then divide it down to get 20MHz. If N is set to '0x00', the VCO will slew to the minimum frequency.
Post-Divider
Q[9:0] are the bits used to program the 10-bit post-dividers on output banks OUT2-6. OUT1 bank does not have a 10-bit post-divider or any other post-
divide along its path. The 10-bit post-dividers will divide down the output banks' frequency with integer values ranging from 1 to 1023.
There is the option to choose between disabling the post-divider, utilizing a div/1, a div/2, or the 10-bit post-divider by using the PM[1:0] bits. Each bank,
except for OUT1, has a set of PM bits. When disabling the post-divider, no clock will appear at the outputs, but will remain powered on. The values are listed
in the table below.
PM[1:0] P Post-Divider
00 disabled
01 div/1
10 div/2
11 Q[9:0] + 2 (Eq. 6)
00
01
10
11
/2
/ (Q+2)
PM[1:0]
/2
To Outputs
VCO
P
Post-Divider Diagram
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INDUSTRIAL TEMPERATURE RANGE
IDT5V9885T
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
Note that the actual 10-bit post-divider value has a 2 added to the integer value Q and the outputs are routed through another div/2 block. The post-divider
should never be disabled unless the output bank will never be used during normal operation. The output frequency range for LVTTL outputs are from 4.9KHz
to 200MHz. The output frequency range for LVPECL/LVDS outputs are from 4.9KHz to 500MHz.
SPREAD SPECTRUM GENERATION
PLL0 and PLL1 support spread spectrum generation capability, which users have the option of turning on and off. Spread spectrum profile, frequency, and
spread are fully programmable (within limits). The programmable spread spectrum generation parameters are TSSC[3:0], NSSC[3:0], SS_OFFSET[5:0],
SD[3:0], DITH, and X2 bits. These bits are in the memory address range of 0x60 to 0x67 for PLL0 and 0x68 to 0x6F for PLL1. The spread spectrum generation
on PLL0 & PLL1 can be enabled/disabled using the TSSC[3:0] bits. To enable spread spectrum, set TSSC > '0' and set NSSC, SD[3:0], SD[5:0], and the
A[3:0] in the total M value accordingly. And to disable, set TSSC = '0'.
TSSC[3:0]
These bits are used to determine the number of phase/frequency detector cycles per spread spectrum cycle (ssc) steps. The modulation frequency can be
calculated with the TSSC bits in conjunction with the NSSC bits. Valid TSSC integer values for the modulation frequency range from 5 to 14.
NSSC[3:0]
These bits are used to determine the number of delta-encoded samples used for a single quadrant of the spread spectrum waveform. All four quadrants
of the spread spectrum waveform are mirror images of each other. The modulation frequency is also calculated based off the NSSC bits in conjunction with the
TSSC bits. Valid NSSC integer values range from 1 to 6.
SS_OFFSET[5:0]
These bits are used to program the fractional offset with respect to the nominal M integer value. For center spread, the SS_OFFSET should be set to '0' so
the spread spectrum waveform is about the nominal M (Mnom) value. For down spread, the SS_OFFSET > '0' so the spread spectrum wavform is about the
(Mideal -1 = Mnom) value. The downspread percentage can be thought of in terms of center spread. For example, a downspread of -1% can also be considered
as a center spread of ±0.5% but with Mnom shifted down by one and offset. The SS_OFFSET has integer values ranging from 0 to 63.
SD[3:0]
These bits are used to shape the profile of the spread spectrum waveform. These are delta-encoded samples of the waveform. There are twelve sets of
SD samples for each PLL. The NSSC bits determine how many of these samples are used for the waveform. The sum of these delta-encoded samples (sigma-
delta-encoded samples) determine the amount of spread and should not exceed (63 - SS_OFFSET). The maximum spread is inversely proportional to the
nominal M integer value.
DITH
This bit is for dithering the sigma-delta-encoded samples. This will randomize the least-significant bit of the input to the spread spectrum modulator. Set the
bit to '1' to enable dithering.
X2
This bit will double the total value of the sigma-delta-encoded-samples which will increase the amplitude of the spread spectrum waveform by a factor of two.
When X2 is '0', the amplitude remains nominal but if set to '1', the amplitude is increased by x2.
The following equations govern how the spread spectrum is set:
T
SSC = TSSC[3:0] + 2 (Eq. 7)
NSSC = NSSC[3:0] * 2 (Eq. 8)
SD[3:0]K = SJ+1(unencoded) - SJ(unencoded) (Eq. 9)
where SJ is the unencoded sample out of a possible 12 and SDK is the delta-encoded sample out of a possible 12.
Amplitude = (2*N[11:0] + A[3:0] + 1) * Spread% / 100 (Eq. 10)
2
if 1 < Amp < 2, then set X2 bit to '1'.
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INDUSTRIAL TEMPERATURE RANGE
IDT5V9885T
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
Modulation frequency:
FPFD = FIN / D (Eq. 11)
FVCO = FPFD * MNOM (Eq. 12)
FSSC = FPFD / (4 * Nssc * Tssc) (Eq. 13)
Spread:
ΣΔ = SD0 + SD1 + SD2 + … + SD11
the number of samples used depends on the NSSC value
ΣΔ ≤ 63 - SS_OFFSET
±Spread% = ΣΔ * 100 (Eq. 14)
64 * (2*N[11:0] + A{3:0} + 1)
±Max Spread% / 100 = 1 / M
NOM or 2 / MNOM (X2=1)
Profile:
Waveform starts with SS_OFFSET, SS_OFFSET + SDJ, SS_OFFSET + SDJ+1, etc.
Spread Spectrum Using Sinusoidal Profile
ΣΔ = 63
(SS_OFFSET = 0)

5V9885TPFGI8

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