CPS-16 Datasheet 47 April 6, 2016
1 Device Overview
The CPS-16, device number IDT80KSW0002, is a serial RapidIO (sRIO)
switch
whose functionality is central to routing packets for distribution among DSPs,
processors, FPGAs, other switches, or any other sRIO-based devices. It may
also be used in serial RapidIO backplane switching. The CPS-16 supports serial
RapidIO packet switching (unicast, multicast, and an optional broadcast) from
any of its 16 input ports to any of its 16 output ports.
2 Features
?
Interfaces - sRIO
–
16 bidirectional serial RapidIO (sRIO) lanes v 1.3
– Port Speeds selectable: 3.125Gbps, 2.5Gbps, or 1.25Gbps
– All lanes support short haul or long haul reach for each PHY speed
– Configurable port count to up to sixteen 1x ports, four 4x ports, or
combinations of 1x and 4x ports (ex. twelve 1x ports and one 4x port)
– Lanes can be configured as individual non-redundant 1x ports, as
part of a redundant 1x port, or as part of a 4x port
– Support for two separate port rates for each quad
– Supports standard 4 levels of priority
– Error management support
?
Interfaces - I
2
C
–
Provides I
2
C port for maintenance and error reporting
– Master or Slave Operation
– Master allows power-on configuration from external ROM
– Master mode configuration with external image compressing and
checksum
?
Performance
–
40 Gbps of peak switching bandwidth
– Non-blocking data flow architecture within each sRIO priority
– Very low latency for all packet length and load condition
– Internal queuing buffer and retransmit buffer
– Standard receiver based physical layer flow control
?
Features
–
Configurable for Cut Through or Store And Forward data flow
– Device configurable through any of sRIO ports, I
2
C, or JTAG
– Packet Trace. Each port provides the ability to match the first 160 bits
of any packet against up to 4 programmable comparison values to
copy the packet to a programmable output trace port
– Packet Filter. Each port also provides the ability to filter the packet
based on comparisons against these same 4 programmable values
mentioned above.
– Supports up to 10 simultaneous multicast masks
– Broadcast support
– Port Loopback Debug Feature
– Software assisted error recovery, supporting hot swap
– Ports may be individually turned off to reduce power
– PMON counters for monitor and diagnostics. Per input port and
output port counters.
– SerDes physical diagnostic registers
– Embedded PRBS generation and detection with programmable poly-
nomials support Bit Error Rate (BER) testing
– 0.13um technology
– Low power dissipation
– Full JTAG Boundary Scan Support (IEEE1149.1 & 1149.6)
– Package: 324-ball grid array, 19mm x 19mm, 1.0mm ball pitch
3 Block Diagram
Figure 1 Block diagram
Maintenance
&
Error
Management
ConfigurationJTAG I
2
C
Serial RapidIO 2.0 Switch
CPS-16
Ln0
Ln1
Ln2
Ln3
Ln5
Ln6
Ln7
Ln4
Ln8
Ln9
Ln10
Ln11
Ln13
Ln14
Ln15
Ln12
Datasheet
80KSW0002
16-Port Serial RapidIO®
Switch
