IDT80KSW0002 Datasheet
CPS-16 Datasheet 47 April 6, 2016
Figure 7 sRIO Lanes Test Load
The characteristic impedance Z0 should be designed for 100 Ohms. An inline capacitor C1 and C2 at each input of the receiver provides AC-coupling
and a DC-block. The IDT recommended and test value is 100nF for each. Thus, any DC bias differential between the two devices on the link is
negated. The differential input resistance at the receiver is designed to be 100 Ohms (per sRIO specification). Thus, R1 and R2 are 50 Ohms each.
Note that V
BIAS is the internal bias voltage of the device’s receiver.
11 Device Performance Figures
Performance Figures
The following table lists the CPS-16’s performance figure. Figures provided here are guaranteed by design and characterization, but are not produc-
tion tested.
Table 4 80KSW0002 Performance Figures
NOTES:
1. Values are guaranteed by characterization, but are not production tested.
2. For those specifications associated with an sRIO transaction, it should be noted that the upper limit to a specification may be dictated by sRIO
priority handling. For example, a maintenance read packet having lower priority may be held off until higher priority packets in queue are serviced. The
user should take into consideration this additional priority-induced delay when examining these specifications. I
2
C and JTAG configuration register
access transactions are always deterministic and follow these specifications identically.
3. “Cycles” refer to internal core clock cycles which are two times the external reference clock (REF_CLK) frequency = 312.5 MHz.
Description Min Typ Max Units Comments
Switch Throughput (Peak) - - 40 Gbps
Switch Throughput (Sustained) - 35 - Gbps
Value shown is for device configured for 3 4X ports, each
running at 3.125Gbps, 276 byte packets at priority 0. Please
contact IDT technical support for figures related to a
specific usage case and traffic conditions.
Switch Latency Jitter (70% switch load)
2
-60-ns
Latency Jitter for the switch lock is the sum of the Physical
layer jitter plus one maintenance packet of contention delay
for a given output port. Worst case for the physical layer is
the jitter caused by the port sync process. This requires 6
32-bite control symbols plus 2 cycles times the port rate.
The figures shown here are for priority 2 packets under 70%
switch loading with an even mix of packets of each priority.
It assumes that no maintenance packets contend on the
output port.
Soft Reset to Receipt of Valid Packets - - 26 us This includes reset time as well as link establishment.
Hard Reset to Receipt of Valid Packets - - 26 us This includes reset time as well as link establishment.
Multicast Map Update Delay 25 - 2000 cycles
3
Z0
Z0
Tx
TXP
TXN
Rx
RXP
RXN
Vbias
C1
C2
R1
R2
