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80KSW0002ALG

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P47
IDT80KSW0002 Datasheet
CPS-16 Datasheet 47 April 6, 2016
Table 18 Long Run Transmitter AC Timing Specifications - 2.5 GBaud
Table 19 Long Run Transmitter AC Timing Specifications - 3.125 GBaud
For each baud rate at which an LP-Serial transmitter is specified to operate, the output eye pattern of the transmitter falls entirely within the unshaded
portion of the Transmitter Output Compliance Mask shown in Transmitter Output Compliance Mask (Figure 15) with the parameters specified in
Transmitter Differential Output Eye Diagram Parameters (Table 17) when measured at the output pins of the device and the device is driving a 100
Ohm +/- 5% differential resistive load. The specification allows the output eye pattern of a LP-Serial transmitter that implements pre-emphasis (to
equalize the link and reduce inter-symbol interference) to only comply with the Transmitter Output Compliance Mask when pre-emphasis is disabled
or minimized.
Symbol Parameter
Range
Unit Notes
Min Max
V
O
Output Voltage -0.40 2.30 Volts
Voltage relative to COM-
MON of either signal com-
prising a differential pair.
V
DIFF PP
Differential Output Voltage 800 1600 mV p-p
J
D
Deterministic Jitter - 0.17 UI p-p
J
T
Total Jitter - 0.35 UI p-p
S
MO
Multiple Output Skew - 1000 ps
Skew at the transmitter
output between lanes of a
multilane link
UI Unit Interval 400 400 ps +/- 100 ppm
Symbol Parameter
Range
Unit Notes
Min Max
V
O
Output Voltage -0.40 2.30 Volts
Voltage relative to COM-
MON of either signal com-
prising a differential pair.
V
DIFF PP
Differential Output Voltage 800 1600 mV p-p
J
D
Deterministic Jitter - 0.17 UI p-p
J
T
Total Jitter - 0.35 UI p-p
S
MO
Multiple Output Skew - 1000 ps
Skew at the transmitter
output between lanes of a
multilane link
UI Unit Interval 320 320 ps +/- 100 ppm
IDT80KSW0002 Datasheet
CPS-16 Datasheet 47 April 6, 2016
Figure 15 Transmitter Output Compliance Mask
Table 20 Transmitter Differential Output Eye Diagram Parameters
Receiver Specifications
LP-Serial receiver electrical and timing specifications are stated in the text and tables of this section.
The receiver input impedance results in a differential return loss better than 10 dB and a common mode return loss better than 6 dB from 100 MHz to
(0.8)*(Baud Frequency).
This includes contributions from on-chip circuitry, the chip package and any off-chip components related to the receiver. AC
coupling components are included in
this requirement. The reference impedance for return loss measurements is 100 Ohm resistive for differential
return loss and 25 Ohm resistive for common mode.
Transmitter Setting V
DIFFmin
(mV) V
DIFFmax
(mV) A (UI) B (UI)
1.25 GBaud Short Range 250 500 0.175 0.39
1.25 GBaud Long Range 400 800 0.175 0.39
2.5 GBaud Short Range 250 500 0.175 0.39
2.5 GBaud Long Range 400 800 0.175 0.39
3.125 GBaud Short Range 250 500 0.175 0.39
3.125 Gbaud Long Range 400 800 0.175 0.39
VDIFFmax
VDIFFmin
-VDIFFmax
-VDIFFmin
0
0AB 1 - A1 - B
1
Time in UI
Transmitter Differential Output Voltage
IDT80KSW0002 Datasheet
CPS-16 Datasheet 47 April 6, 2016
Table 21 Receiver AC Timing Specifications - 1.25 GBaud
NOTE:
1. Total jitter is composed of three components, deterministic jitter, random jitter and single frequency sinusoidal jitter. The sinusoidal jitter may have
any amplitude and frequency in the unshaded region of Figure 16. The sinusoidal jitter component is included to ensure margin for low frequency jitter,
wander, noise, crosstalk and other variable system effects.
Table 22 Receiver AC Timing Specifications - 2.5 GBaud
NOTE:
1. Total jitter is composed of three components, deterministic jitter, random jitter and single frequency sinusoidal jitter. The sinusoidal jitter may have
any amplitude and frequency in the unshaded region of Figure 16. The sinusoidal jitter component is included to ensure margin for low frequency jitter,
wander, noise, crosstalk and other variable system effects.
Symbol Parameter
Range
Unit Notes
Min Max
V
IN
Differential Input Voltage 200 1600 mV p-p Measured at receiver
J
D
Deterministic Jitter Tolerance 0.37 - UI p-p Measured at receiver
J
DR
Combined Deterministic and
Random Jitter Tolerance
0.55 - UI p-p Measured at receiver
J
T
Total Jitter Tolerance
(1)
0.65 - UI p-p Measured at receiver
S
MI
Multiple Input Skew - 24 ns
Skew at the receiver input
between lanes of a multi-
lane link
BER Bit Error Rate 10
-12
UI Unit Interval 800 800 ps +/- 100 ppm
Symbol Parameter
Range
Unit Notes
Min Max
V
IN
Differential Input Voltage 200 1600 mV p-p Measured at receiver
J
D
Deterministic Jitter Tolerance 0.37 - UI p-p Measured at receiver
J
DR
Combined Deterministic and
Random Jitter Tolerance
0.55 - UI p-p Measured at receiver
J
T
Total Jitter Tolerance
(1)
0.65 - UI p-p Measured at receiver
S
MI
Multiple Input Skew - 24 ns
Skew at the receiver input
between lanes of a multi-
lane link
BER Bit Error Rate 10
-12
UI Unit Interval 400 400 ps +/- 100 ppm
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P47

80KSW0002ALG

Mfr. #:
Buy 80KSW0002ALG
Manufacturer:
IDT
Description:
Switch ICs - Various 80KSW0002 Central Packet SW-16 ports
Lifecycle:
New from this manufacturer.
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