IDT80KSW0002 Datasheet
CPS-16 Datasheet 47 April 6, 2016
Each sRIO port provides a packet trace capability. For any packet received by a port, a comparison between the first 160 bits and up to four configu-
rable values can be performed. A match against any of these parameters will result in a copy of the packet and a route of the packet to a configurable
ouput port. This feature can be used as a tactical function to track user data or in a debug environment to test how specific packets are moving
through the platform.
Each sRIO port also provides a packet filter capability. For any packet received by a port, a comparison between the first 160 bits and up to the same
four configurable values mentioned above can be performed. A match against any of these parameters will result in the packet being filtered.
7 Interface Overview
Figure 3 Diagram of the CPS-16 Interfaces
sRIO Ports
The sRIO interfaces are the main communication ports on the chip. These ports are compliant with the serial RapidIO v. 1.3 specifications. Please
refer to the serial RapidIO specifications for full detail [2-10].
The device provides 16 differential dual simplex transceivers dedicated to sRIO I/O. These can be independently configured to run in various configu-
rations as 1x- or 4x-ports. The CPS-16 supports a maximum of 4 times 4x-ports, or 16 times 1x-ports, as well as combinations of both 1x- and 4x-
ports.
The device has a proprietary implementation which we refer to as an “Enhanced Quad.” An Enhanced Quad can be operated in standard sRIO mode
like the standard quads. Additionally the Enhanced Quad can be register-configured to run as 4 independent 1x-ports - any of which can be enabled at
a given time. In this manner, the user has the flexibility to use one, multiple, or all four lanes in 1x-mode. For example, lanes 0 - 3 are programmable
into one 4x- or four 1x-ports. This is unlike the standard sRIO port implementation that, when configured as a 1x-port, renders the remaining 3 possible
connections unused.
The device control of each of lane parameters (data rate, transmitter pre-emphasis, drive strength) can be separately configured, such that the char-
acteristics for lanes 0 and 1 can be different from those for lanes 2 and 3 in one quad. The ability to control reset and initialization of lanes 0 and 1
versus lanes 2 and 3 separately is also provided. So each 2 lanes (lanes 0, 1 and lanes 3,4) at the granularity of the half quad can be programmed to
run independently at 1.25, 2.5, or 3.125Gbps and handle long or short haul serial transmission per RIO serial specification
IDT CPS-16
16 Differential sRIO Lanes
1.25, 2.5, or 3.125 Gbps
I2C Interface
400KHz
JTAG Interface
RST
REF_CLK
IRQ
Rext
SPD[1:0]
