IDT80KSW0002 Datasheet
CPS-16 Datasheet 47 April 6, 2016
I
2
C AC Electrical Specifications
Table 11 Specifications of the SDA and SCL bus lines for F/S-mode I
2
C -bus devices
NOTES:
1.
For more information, see the I
2
C-Bus specification by Philips Semiconductor [1].
2. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V
IHMIN of the SCL signal) to bridge the unde-
fined region of the falling edge of SCL.
3. The maximum t
HD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCL signal.
4. A Fast-mode I
2
C-bus device can be used in a Standard-mode I
2
C-bus system, but the requirement tSU;DAT > 250 ns must then be met. This will
automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL
signal, it must output the next data bit to the SDA line t
RMAX + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I
2
C-bus specifica-
tion) before the SCL line is released.
Signal Symbol
Reference
Edge
Standard
Mode
Fast
Mode
Unit
Min Max Min Max
I
2
C
(1,4)
SCL f
SCL
none 0 100 0 400 kHz
t
HD;STA
4.0 0.6 s
t
R
1000 300 s
t
F
300 300 s
SDA
(2,3)
t
SU;DAT
SCL rising 250 100 s
t
HD;DAT
03.450 0.9 s
t
R
1000 10 300 s
t
F
300 10 300 s
Start or repeated start
condition
t
SU;STA
SDA falling 4.7 0.6 s
t
SU;STO
4.0 0.6 s
Stop condition t
SU;STO
SDA rising 4.0 0.6 s
Bus free time between
a stop and start condi-
tion
t
BUF
4.7 1.3 s
Capacitive load for
each bus line
C
b
400 400 pF
IDT80KSW0002 Datasheet
CPS-16 Datasheet 47 April 6, 2016
I
2
C Timing Waveforms
Figure 12 I
2
C Timing Waveforms
14 Interrupt (IRQ) Electrical Specifications
At recommended operating conditions with VDD3 = 3.3V ± 5%
Table 12 IRQ Electrical Specifications (VDD3 = 3.3V ± 5%)
t
SU;STO
t
HD;STA
t
SU;STA
t
SU;DAT
t
HD;DAT
t
HIGH
t
HD;STA
t
LOW
SDA
SCL
t
BUF
Parameter Symbol Min Max Unit
Low level output voltage (I
OL
= 4mA, V
DD3
=
Min.)
V
OL
0 0.4 V
Output fall time from V
IH(min)
to V
IL(max)
with a
bus capacitance from 10pF to 400pF
t
OF
- 25 ns
Input current each I/O pin (input voltage is
between 0.1 x V
DD3
and 0.9 x V
DD3
(max))
I
I
-10 10 uA
Capacitance for IRQ C
I
- 10 pF
IDT80KSW0002 Datasheet
CPS-16 Datasheet 47 April 6, 2016
At recommended operating conditions with VDD3 = 2.5V ± 100mV
Table 13 IRQ Electrical Specifications (VDD3 = 2.5V ± 100mV)
Figure 13 IRQ
Timing Diagram
The IRQ pin is an open-drain driver. IDT recommends a weak pull-up resistor (2-10k Ohm) be placed on this pin to VDD3. The IRQ pin goes active low
when any special error filter error flag is set, and is cleared when all error flags are reset. Please refer to the device user’s manual for full detail.
15 Serial RapidIO Ports
Overview
The CPS-16’s SERDES are in full compliance to the RapidIO AC specifications for the LP-Serial physical layer [5]. This section provides those
specifications for reference. The electrical specifications cover both single and multiple-lane links. Two transmitters (short run and long run) and a
single receiver are specified for each of three baud rates, 1.25, 2.50, and 3.125 GBaud.
Two transmitter specifications allow for solutions ranging from simple chip-to-chip interconnect to driving two connectors across a backplane. A single
receiver specification is given that will accept signals from both the short run and long run transmitter specifications.
The short run transmitter setting should be used mainly for chip-to-chip connections on either the same printed circuit board or across a single
connector. This covers the case where connections are made to a mezzanine (daughter) card. The minimum swings of the short run specification
reduce the overall power used by the transceivers.
The long run transmitter specifications use larger voltage swings that are capable of driving signals across backplanes. This allows a user to drive
signals across two connectors and a backplane. The CPS-16 can drive beyond the specification distance of at least 50 cm at all baud rates. Please
use IDT’s Simulation Kit IO models to determine reach and signal quality for a given PCB design.
Parameter Symbol Min Max Unit
Low level output voltage (I
OL
= 2mA, V
DD3
=
Min.)
V
OL
0 0.4 V
Output fall time from V
IH(min)
to V
IL(max)
with a
bus capacitance from 10pF to 400pF
t
OF
- 25 ns
Input current each I/O pin (input voltage is
between 0.1 x V
DD3
and 0.9 x V
DD3
(max))
I
I
-10 10 uA
Capacitance for IRQ C
I
- 10 pF

80KSW0002ALG

Mfr. #:
Manufacturer:
IDT
Description:
Switch ICs - Various 80KSW0002 Central Packet SW-16 ports
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New from this manufacturer.
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