IDT80KSW0002 Datasheet
CPS-16 Datasheet 47 April 6, 2016
3) If CPS-16 polls configuration image from external memory
– CPS-16 addresses the memory.
– Memory transmits the data.
– CPS-16 gets the data.
All signaling is fully compliant with I
2
C. Full detail of signaling can be found in the Philips I
2
C specification [1]. Standard signalling and timing
waveforms are shown below.
Interfacing to Standard-, Fast-, and Hs-mode Devices
The CPS-16 supports Fast / Standard (F/S) modes of operation. Per I
2
C specification, in mixed speed communication the CPS-16 supports Hs- and
Fast-mode devices at 400 kbit/s, and Standard-mode devices at 100 kbit/s. Please refer to the I
2
C specification for detail on speed negotiation on a
mixed speed bus.
CPS-16 Specific Memory Access (Slave mode)
There is a CPS-16 specific I
2
C memory access implementation. This implementation is fully I
2
C compliant. It requires the memory address to be
explicitly specified during writes. This provides directed memory accesses through the I
2
C bus. Subsequent reads always begin at the address
specified during the last write.
The write procedure requires the 3-Bytes (22-bits) of memory address to be provided following the device address. Thus, the following are required:
device address – one or two bytes depending on 10-bit / 7-bit addressing, memory address – 3 bytes yielding 22-bits of memory address, and a 32-
bit data payload – 4 byte words. To remain consistent with sRIO standard maintenance packet memory address convention, the I
2
C memory address
provided must be the 22MSBs. Since I
2
C writes to memory apply to double words (32-bits), the 2 LSBs are DON’T CARE as the LSBs correspond to
word and byte pointers.
The read procedure has the memory address section of the transfer removed. Thus, to perform a read, the proper access would be to perform a write
operation and issue a repeated start after the acknowledge bit following the third byte of memory address. Then, the master would issue a read
command selecting the CPS-16 through the standard device address procedure with the R/W bit high. Note that in 10-bit device address mode
(ADS=1), only the two MSBs need be provided during this read. Data from the previously loaded address would immediately follow the device
address protocol. It is possible to issue a stop or repeated start anytime during the write data payload procedure, but must be before the final
acknowledge (i.e. canceling the write before the actual write operation is completed and performed). Also, the master would be allowed to access
other devices attached to the I
2
C bus before returning to select the CPS-16 for the subsequent read operation from the loaded address.
Figures
Figure 8 Write protocol with 10-bit Slave Address (ADS =1). I
2
C writes to memory align on 32-bit word boundaries, thus the 22 address MSBs must
be provided while the 2 LSB’s associated with word and byte pointers are DON’T CARE and are therefore not transmitted.
5686 d 05
Device
Address
[9:8]
11110
0
AA AA A
Memory
Address
[21:16]
R/W Bit (R=1, W=0)
8 17 263544
Memory address loaded is mem_addr[21:0]
XX
A 000
Device
Address
[7:0]
Memory
Address
[15:8]
Memory
Address
[7:0]
0
Data
Word #1
MSB Byte
Incoming data will be written
to mem_addr[21:0]
