IDT80KSW0002 Datasheet
CPS-16 Datasheet 47 April 6, 2016
16 Reference Clock
The differential reference clock (REF_CLK+/-) is used to generate the sRIO PHY and internal clocks used in the CPS-16.
Reference Clock Electrical Specifications
The reference clock is 156.25 MHz, and is AC-coupled with the following electrical specifications:
Figure 18 REF_CLK Representative Circuit
Table 25 Input Reference Clock Jitter Specifications
The reference clock wander should not be more than 100ppm (for 156.25 MHz, this is +/-15.625 KHz). This requirement comes from the sRIO
specification that outgoing signals from separate links which belong to the same port should not be separated more than 100ppm.
Note that the series capacitors are discretes that must be placed external to the device’s receivers. All other elements are associated with the input
structure internal to the device. V
BIAS is generated internally.
Name Description Min Nom Max Units
REF_CLK REF_CLK clock running at 156.25Mhz -100
----
+100 ppm
Phase Jitter (rms) Phase Jitter (rms) (1MHz - 20MHz)
-----
-----
2ps
tDUTY_REF REF_CLK duty cycle 40 50 60 %
tRCLK/tFCLK Input signal rise/fall time (20%-80%) 200 500 650 ps
vIN_CML Differential peak-peak REF_CLK input swing 400
----
2400 mV
RL_CLK Input termination resistance 40 50 60 ohm
LI_CLK Input inductance
-----
-----
4nH
CI_CLK Input capacitance
-----
-----
5pF
5686 drw07
REF_CLK_P
REF_CLK_N
REF_CLK
L
I
,CLK
C
I
,CLK
V
BIAS
,CLK
L
I
,CLK
C
I
,CLK
R
L
,CLK
R
L
,CLK
+
-
