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80KSW0002ALG

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P47
IDT80KSW0002 Datasheet
CPS-16 Datasheet 47 April 6, 2016
At recommended operating conditions with VDD3 = 2.5V ± 100mV
Table 32 JTAG DC Electrical Specifications (VDD3 = 2.5V ± 100mV )
JTAG AC Electrical Specifications
(2,3,4)
Table 33 JTAG AC Electrical Specifications
NOTES:
1. Guaranteed by design.
2. Refer to AC Electrical Test Conditions stated earlier in this document.
3. JTAG operations occur at one speed (10MHz). The base device may run at any speed specified in this
datasheet.
Parameter Symbol Min Max Unit
2.5V Supply Voltage V
DD3
2.4 2.6 V
Ground V
SS
0 0 V
Input high voltage level V
IH
1.7 V
DD3(max)
+ 0.1 V
Input low voltage level V
IL
-0.3 0.7 V
Output Low Voltage (IOL = 2mA, V
DD3
= Min.) V
OL
- 0.4 V
Output High Voltage (IOH = -2mA, V
DD3
=
Min.)
V
OH
2.0 - V
Input current for JTAG pins (input voltage is
between 0.1 x V
DD3
and 0.9 x V
DD3
(max)
I
LI
-30 30 uA
Capacitance for each Input pin C
IN
- 8 pF
Capacitance for each I/O or Output pin C
OUT
- 10 pF
80KSW0002
Symbol Parameter Min. Max. Units
t
JCYC
JTAG Clock Input Period 100
____
ns
t
JCH
JTAG Clock HIGH 40
____
ns
t
JCL
JTAG Clock Low 40
____
ns
t
JR
JTAG Clock Rise Time
____
3
(1)
ns
t
JF
JTAG Clock Fall Time
____
3
(1)
ns
t
JRST
JTAG Reset 50
____
ns
t
JRSR
JTAG Reset Recovery 50
____
ns
t
JCD
JTAG Data Output
____
25 ns
t
JDC
JTAG Data Output Hold 0
____
ns
t
JS
JTAG Setup 15
____
ns
t
JH
JTAG Hold 15
____
ns
5686 tbl 02
IDT80KSW0002 Datasheet
CPS-16 Datasheet 47 April 6, 2016
JTAG Timing Waveforms
Figure 27 JTAG Timing Specifications
NOTES:
1. Device inputs = All device inputs except TDI, TMS, and TRST.
2. Device outputs = All device outputs except TDO.
18 Reset & Initialization
Power Supply Sequencing
The CPS-16 does not require specific power sequencing between any of the core and I/O supplies.
Reset Pin and Timing
Figure 28 Reset Timing
To reset the device, first reset signal has to be de-asserted (Reset Low), and it is asserted after 5 REF_CLK cycles. 4096 REF_CLK cycles later, the
device completes the reset process. Once completed, access to the CPS-16 from any and all interfaces is possible and the CPS-16 is fully functional.
Control and data traffic will not be accepted by the CPS-16 until this process is fully completed.
TCK
Device Inputs
(1)
/
TDI/TMS
Device Outputs
(2)
/
TDO
TRST
t
JCD
t
JDC
t
JRST
t
JS
t
JH
t
JCYC
t
JRSR
t
JF
t
JCL
t
JR
t
JCH
5686 drw 08
,
RST 5 REF_CLK Cycles 4096 REF_CLK Cycles
IDT80KSW0002 Datasheet
CPS-16 Datasheet 47 April 6, 2016
Table 34 CPS-16 Reset Port Configuration
Speed Select (SPD[1:0])
There are 2 port speed select pins. These pins are used to chose the initial speed on sRIO ports. The selection table is given below:
Table 35 Port Speed Selection Pin Values
At power-up the CPS-16 is configured as with 16 non-redundant 1x ports. All ports are configured with each link running at 1.25, 2.5, or 3.125 Gbps
(depending on the SPD[1:0] pins).
An end-point connected to the CPS-16 can then reprogram all the ports to the desired configuration. All ports are configured as long run at start up
because it will allow the port to communicate to either a short run or long run port on the CPU.
Initialization of sRIO Switching
At the initialization all values in the route table are programmed as default route. But the CPS-16 accepts maintenance packets. These maintenance
packets may be used to configure the CPS-16.
Lane# Quad#
Quad
Type
Default
on Reset
1x-Ports Only
Port Numbering
4x-Ports Only
Port Numbering
0
0 Enhanced Enhanced
0
0
11
22
33
4
1 Enhanced Enhanced
4
1
55
66
77
8
2 Enhanced Enhanced
8
2
99
10 10
11 11
12
3 Enhanced Enhanced
12
3
13 13
14 14
15 15
Value on the Pins (SPD1, SPD0) Ports Rate
00 1.25Gbps
01 2.5Gbps
10 3.125Gbps
11 Reserved
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P47

80KSW0002ALG

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Buy 80KSW0002ALG
Manufacturer:
IDT
Description:
Switch ICs - Various 80KSW0002 Central Packet SW-16 ports
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New from this manufacturer.
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