IDT80KSW0002 Datasheet
CPS-16 Datasheet 47 April 6, 2016
SAMPLE/PRELOAD
The sample/preload instruction has a dual use. The primary use of this instruction is for preloading the boundary scan register prior to enabling the
EXTEST instruction. Failure to preload will result in unknown random data being driven onto the output pins when EXTEST is selected. The secondary
function of SAMPLE/PRELOAD is for sampling the system state at a particular moment.
BYPASS
The BYPASS instruction is used to truncate the boundary scan register to a single bit in length. During system level use of the JTAG, the boundary
scan chains of all the devices on the board are connected in series. In order to facilitate rapid testing of a given device, all other devices are put into
BYPASS mode. Therefore, instead of having to shift 70 times to get a value through the CPS-16, the user only needs to shift one time to get the value
from TDI to TDO. When the TAP controller passes through the CAPTURE-DR state, the value in the BYPASS register is updated to be 0.
If the device being used does not have an IDCODE register, then the BYPASS instruction will automatically be selected into the instruction register
whenever the TAP controller is reset. Therefore, the first value that will be shifted out of a device without an IDCODE register is always 0. Devices
such as the CPS-16 that include an IDCODE register will automatically load the IDCODE instruction when the TAP controller is reset, and they will
shift out an initial value of 1. This is done to allow the user to easily distinguish between devices having IDCODE registers and those that do not.
CLAMP
This instruction, listed as optional in the IEEE 1149.1 JTAG Specifications, allows the boundary scan chain outputs to be clamped to fixed values.
When the clamp instruction is issued, the scan chain will bypass the CPS-16 and pass through to devices further down the scan chain.
IDCODE
The IDCODE instruction is automatically loaded when the TAP controller state machine is reset either by the use of the TRST signal or by the appli-
cation of a ‘1’ on TMS for five or more cycles of TCK as per the IEEE Std 1149.1 specification. The least significant bit of this value must always be 1.
Therefore, if a device has a IDCODE register, it will shift out a 1 on the first shift if it is brought directly to the SHIFT-DR TAP controller state after the
TAP controller is reset. The board- level tester can then examine this bit and determine if the device contains a DEVICE_ID register (the first bit is a 1),
or if the device only contains a BYPASS register (the first bit is 0).
However, even if the device contains an IDCODE register, it must also contain a BYPASS register. The only difference is that the BYPASS register will
not be the default register selected during the TAP controller reset. When the IDCODE instruction is active and the TAP controller is in the Shift-DR
state, the thirty-two bit value that will be shifted out of the device-ID register is 0x0035B067.
EXTEST PULSE
This IEEE 1149.6 instruction applies only to the AC-coupled pins. All DC pins will perform as if the IEEE Std 1149.1 EXTEST instruction is operating
whenever the EXTEST_PULSE instruction is effective.
Bit(s) Mnemonic Description R/W Reset
0 reserved reserved 0x1 R 1
11:1 Manuf_ID Manufacturer Identity (11 bits)
IDT 0x33
R0x33
27:12 Part_number Part Number (16 bits)
This field identifies the part number of the processor derivative.
For the CPS-16 this value is: 0x35B
Rimpl.
dep.
31:28 Version Version (4 bits)
This field identifies the version number of the processor deriva-
tive.
For the CPS-16, this value is 0x0035B067
Rimpl.
dep.
Table 28 System Controller Device Identification Register
Version Part Number Vendor ID LSB
0000 0000|0011|0101|1011 0000|0110|011 1
Table 29 System Controller Device ID Instruction Format
