80KSW0002ALG Datasheet 80KSW0002ALG, 80KSW0002ALGI, 80KSW0002ALG8 | P10-P12

IDT80KSW0002 Datasheet

CPS-16 Datasheet 47 April 6, 2016

Switch Latency in “Store-and-Forward” mode

Table 5 Switch Latency Table (Store-and-Forward mode)

1) Values are guaranteed by characterization, but are not production tested.

2) For those specifications associated with an sRIO transaction, it should be noted that the upper limit to a specification may be dictated by sRIO

priority handling. For example, a maintenance read packet having lower priority may be held off until higher priority packets in queue are serviced.

The user should take into consideration this additional priority-induced delay when examining these specifications. I

C and JTAG transactions are

always deterministic and follow these specifications identically.

3) Switch latency is a statistical function, which typically increases with increased traffic loading on the switch. Values shown in Table 5 are for

single input port to single output port with matching input and output port rates in “Store-and-Forward” mode, no other switch loading. The switch

latency in “Store-and-Forward” packet forward methodology is also a strong function of port rate. For specific values under other specific applica-

tion usage scenarios and traffic conditions, please contact IDT technical support.

Switch Latency in “Cut-Through” mode

Table 6 Switch Latency Table (Cut-Through mode)

1) Values shown in Table 6 are typical for single input port to single output port with matching input and output port rates in “Cut-Through” mode, no

other switch loading. For specific values under other specific application usage scenarios and traffic conditions, please contact IDT technical

support.

Note:

In "Store-and-Forward" mode and "Cut-Through" mode when trace and filter are enabled at the same time, the latency for packets sent to the

trace port will increase by the time taken to send 20 bytes into the port ([20 bytes * 8 ] * 1/[port_speed * 0.8]). The latency for other traffic flow will

be unaffected.

Pay Load Size 1.25GHz 2.5GHz 3.125GHz

1X 4X 1X 4X 1X 4X

8 Byte 456 ns 343 ns 277 ns 225 ns 246 ns 209 ns

16 Byte 517 ns 360 ns 311 ns 231 ns 267 ns 213 ns

32 Byte 652 ns 435 ns 375 ns 272 ns 320 ns 239 ns

64 Byte 902 ns 500 ns 501 ns 305 ns 422 ns 263 ns

128 Byte 1425 ns 722 ns 757 ns 417 ns 630 ns 352 ns

256 Byte 2451 ns 1071 ns 1273 ns 590 ns 1035 ns 492 ns

Multicast Event

Control Symbol

115 ns 105 ns 60 ns 55 ns 50 ns 45 ns

Pay Load Size 1.25GHz 2.5GHz 3.125GHz

1X 4X 1X 4X 1X 4X

8 Byte 366 ns 322 ns 244 ns 216 ns 208 ns 199 ns

16 Byte 363 ns 324 ns 234 ns 215 ns 206 ns 197 ns

32 Byte 365 ns 316 ns 232 ns 215 ns 205 ns 198 ns

64 Byte 365 ns 318 ns 234 ns 219 ns 204 ns 198 ns

128 Byte 372 ns 314 ns 233 ns 217 ns 210 ns 196 ns

256 Byte 371 ns 312 ns 238 ns 216 ns 205 ns 195 ns

IDT80KSW0002 Datasheet

CPS-16 Datasheet 47 April 6, 2016

12 Typical Power Figures

Typical power draw for the 80KSW0002 is approximately 3.0W total for all ports enabled as 4 4x @ 3.125G under 50% switch load. The following table

provides power figures on a per-block basis. An estimate of the device power figure for a given application usage can be determined by using the

“CPS Power Calculator” modeling tool available on www.IDT.com.

Table 7 Typical Power Figures

Condition: VDD = 1.2V, VDDS = 1.2V, VDDA = 1.2V, VDD3 = 3.3V @ Room temperature 25

Maximum peak sustained power draw for the 80KSW0002 is 4.1W total (2.49W for V

DD, 0.81W for VDDS, 0.54W for VDDA and 0.26W for VDD3) for all

ports enabled as 16 1x @ 3.125G under 100% switch load at the max operational voltage specification(1.2V+5%=1.26V, 3.3V+5%=3.45V) across full

temperature and process range.

Description Typical Units Supply Comments

SerDes 1x @ 1.25G 45 mW V

DDS

, V

DDA

Analog SerDes power consumption (V

DDS

and V

DDA

). This does not

include the sRIO quad power consumption.

SerDes 1x @ 2.5G 60 mW V

DDS

, V

DDA

Analog SerDes power consumption (V

DDS

and V

DDA

). This does not

include the sRIO quad power consumption.

SerDes 1x @ 3.125G 75 mW V

DDS

, V

DDA

Analog SerDes power consumption (V

DDS

and V

DDA

). This does not

include the sRIO quad power consumption.

SerDes 4x @ 1.25G 200 mW V

DDS

, V

DDA

Analog SerDes power consumption (V

DDS

and V

DDA

). This does not

include the sRIO quad power consumption.

SerDes 4x @ 2.5G 220 mW V

DDS

, V

DDA

Analog SerDes power consumption (V

DDS

and V

DDA

). This does not

include the sRIO quad power consumption.

SerDes 4x @ 3.125G 245 mW V

DDS

, V

DDA

Analog SerDes power consumption (V

DDS

and V

DDA

). This does not

include the sRIO quad power consumption.

JTAG Block Enable 100 mW V

, V

DD3

Configuration Register Access only. Max interface speed(10MHz).

I2C Block Enable 20 mW V

, V

DD3

Configuration Register Access only. Max interface speed (400KHz).

Switch Block (max traffic) 416 mW V

Switch block only. All ports enabled and sending traffic at max aggre-

gate throughput for the switch block.

Standby Power @1.25G 1315 mW V

Part powered up, reset, all links up (reset configuration), no traffic

Standby Power @1.25G 214 mW V

DD3

Part powered up, reset, all links up (reset configuration), no traffic

Standby Power @1.25G 498, 349 mW V

DDS

, V

DDA

Part powered up, reset, all links up (reset configuration), no traffic

Quiescent Power 1200 mW V

Minimum possible operational power draw. All ports disable, I2C and

JTAG signals static.

Quiescent Power 214 mW V

DD3

Minimum possible operational power draw. All ports disable, I2C and

JTAG signals static.

Quiescent Power 37, 32 mW V

DDS

, V

DDA

Minimum possible operational power draw. All ports disable, I2C and

JTAG signals static.

Reset Power 324 mW V

Peak power during RESET of the device.

Reset Power 210 mW V

DD3

Peak power during RESET of the device.

Reset Power 35, 27 mW V

DDS

, V

DDA

Peak power during RESET of the device.

Peak sustained Power 2077 mW V

All sRIO ports enabled at maximum speed, maximum traffic to the

switch.

Peak sustained Power 214 mW V

DD3

All sRIO ports enabled at maximum speed, maximum traffic to the

switch.

Peak sustained Power 671, 455 mW V

DDS

, V

DDA

All sRIO ports enabled at maximum speed, maximum traffic to the

switch

IDT80KSW0002 Datasheet

CPS-16 Datasheet 47 April 6, 2016

13 I

C-Bus

The CPS-16 is compliant with the I

C specification [1]. This specification provides all functional detail and electrical specifications associated with the

C bus. This includes signaling, addressing, arbitration, AC timing, DC specifications, and other details.

The I

C bus is comprised of Serial Data (SDA) and Serial Clock (SCL) pins. It can be used to attach a CPU or a configuration memory. The I

interface supports Fast/Standard (F/S) mode (400/ 100 kHz).

C master mode and slave mode

The CPS-16 device supports both master mode and slave mode. It’s selected by MM static configuration pin. Refer to following for signaling and

operation.

C Device Address

The device address for the CPS-16 is fully pin-defined by 10 external pins while in slave mode. This provides full flexibility in defining the slave

address to avoid conflicting with other I

C devices on a given bus. The CPS-16 may be operated as either a 10-bit addressable device or a 7-bit

addressable device based on another external pin, address select (ADS). If the ADS pin is tied to Vdd, then the CPS-16 operates as a 10-bit

addressable device and the device address will be defined as ID[9:0]. If the ADS pin is tied to GND, then the CPS-16 operates as a 7-bit addressable

device with the device address defined by ID[6:0]. The addressing mode must be established at power-up and remain static throughout operation.

Dynamic changes will result in undetermined behavior.

Table 8 I

C static address selection pin configuration

All of the CPS-16’s registers are addressable through I

C. These registers are accessed via 22-bit addresses and 32-bit word boundaries though

standard reads and writes. These registers may also be accessed through the sRIO and JTAG interfaces.

Signaling

Communication with the CPS-16 on the I

C bus follows these three cases:

1) Suppose a master device wants to send information to the CPS-16:

– Master device addresses CPS-16 (slave)

– Master device (master-transmitter), sends data to CPS-16 (slave- receiver)

– Master device terminates the transfer

2) If a master device wants to receive information from the CPS-16:

– Master device addresses CPS-16 (slave)

– Master device (master-receiver) receives data from CPS-16 (slave- transmitter)

– Master device terminates the transfer.

C Address Bit (pin_addr)

ID0 0

ID1 1

ID2 2

ID3 3

ID4 4

ID5 5

ID6 6

ID7 7 (don’t care in 7-bit mode)

ID8 8 (don’t care in 7-bit mode)

ID9 9 (don’t care in 7-bit mode)

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80KSW0002ALG

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Switch ICs - Various 80KSW0002 Central Packet SW-16 ports

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80KSW0002ALG

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