1. General description
The P89CV51RB2/RC2/RD2 are three types of 80C51 microcontroller with respectively
16 kB/32 kB/64 kB flash and 1 kB of data RAM. These devices are designed to be drop-in
and software-compatible replacements for the popular P89C51RB2/RC2/RD2 devices.
Both the In-System Programming (ISP) and In-Application Programming (IAP) boot codes
are upward compatible.
Additional features of the P89CV51RB2/RC2/RD2 devices compared to the
P89C51RB2/RC2/RD2 are the inclusion of an SPI interface, larger RAM size, and the
ability to erase code memory in 128-B page blocks.
The IAP capability combined with the 128-B page size allows for efficient use of the code
memory for non-volatile data storage.
2. Features
2.1 Principal features
n Supports 12-clock (default) or 6-clock mode selection via ISP or parallel programmer
n 6-clock/12-clock mode programmable “on-the-fly” by an SFR bit
n Peripherals (PCA, timers, UART) may use either 6-clock or 12-clock mode while the
CPU is in 6-clock mode
n 128-B page erase for efficient use of code memory as non-volatile data storage
n 0 MHz to 40 MHz operating frequency in 12× mode, 20 MHz in 6× mode
n 16/32/64 kB of on-chip flash user-code memory with ISP and IAP
n 1 kB RAM
n SPI (Serial Peripheral Interface) and enhanced UART
n PCA (Programmable Counter Array) with PWM and capture/compare functions
n Three 16-bit timers/counters
2.2 Additional features
n Four 8-bit I/O ports
n WatchDog Timer (WDT)
n 30 ms page erase, 150 ms block erase
n PLCC44 and TQFP44 packages
n Ten interrupt sources with four priority levels
n Second DPTR register
n Low EMI mode (ALE inhibit)
P89CV51RB2/RC2/RD2
8-bit 80C51 5 V low power 64 kB flash microcontroller with
1 kB RAM, SPI, 6-clock CPU with 6/12-clock peripherals
Rev. 03 — 25 August 2009 Product data sheet
P89CV51RB2_RC2_RD2_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 25 August 2009 2 of 76
NXP Semiconductors
P89CV51RB2/RC2/RD2
80C51 with 1 kB RAM, SPI
n Power-down mode with external interrupt wake-up
n Idle mode
2.3 Comparison to P89C51RB2/RC2/RD2 devices
n SPI: The P89CV51RB2/RC2/RD2 devices have an SPI interface that was not present
on the P89C51RB2/RC2/RD2 devices.
n Smaller block size: The page size decreased from 4 kB to 128 B. These smaller
pages can be erased and reprogrammed using IAP function calls, which makes
practical use of code memory for non-volatile data storage. A page is erased in 30 ms
or less. IAP and ISP code both support 128-B page operations. The IAP and ISP code
uses multiple page-erase operations to emulate the erasing of larger block sizes (8 kB
and 16 kB) to maintain firmware compatibility.
n Status bit replaces Status byte: Automatic entry into ISP mode following a reset is
now controlled by one status bit. Its operation is almost identical to that used by the
previous devices, which was based on the zero/non-zero value of the status byte.
n Faster block erase: The erase time for the entire user-code memory of the
P89CV51RB2/RC2/RD2 devices is 150 ms, which is a significant improvement.
n Larger RAM size: RAM size increased from 512 B to 1 kB.
3. Ordering information
3.1 Ordering options
Table 1. Ordering information
Type number Package
Name Description Version
P89CV51RB2FA PLCC44 plastic leaded chip carrier; 44 leads SOT187-2
P89CV51RB2FBC TQFP44 plastic thin quad flat package; 44 leads; body
10 × 10 × 1.0 mm
SOT376-1
P89CV51RC2FA PLCC44 plastic leaded chip carrier; 44 leads SOT187-2
P89CV51RC2FBC TQFP44 plastic thin quad flat package; 44 leads; body
10 × 10 × 1.0 mm
SOT376-1
P89CV51RD2FA PLCC44 plastic leaded chip carrier; 44 leads SOT187-2
P89CV51RD2FBC TQFP44 plastic thin quad flat package; 44 leads; body
10 × 10 × 1.0 mm
SOT376-1
Table 2. Ordering options
Type number Flash
memory
RAM Temperature
range
Frequency
P89CV51RB2FA 16 kB 1 kB 40 °C to +85 °C 0 MHz to 40 MHz
P89CV51RB2FBC
P89CV51RC2FA 32 kB 1 kB
P89CV51RC2FBC
P89CV51RD2FA 64 kB 1 kB
P89CV51RD2FBC
P89CV51RB2_RC2_RD2_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 25 August 2009 3 of 76
NXP Semiconductors
P89CV51RB2/RC2/RD2
80C51 with 1 kB RAM, SPI
4. Block diagram
Fig 1. Block diagram
HIGH PERFORMANCE
80C51 CPU
16 kB/32 kB/64 kB
CODE FLASH
1 kB
DATA RAM
PORT 1
PORT 0
OSCILLATOR
internal
bus
CRYSTAL
OR
RESONATOR
002aac960
UART
PCA
PROGRAMMABLE
COUNTER ARRAY
PORT 2
TIMER 2
TIMER 0
TIMER 1
SPI
XTAL1
XTAL2
WATCHDOG TIMER
PORT 3
P3[7:0]
P2[7:0]
P1[7:0]
P0[7:0]
TXD
RXD
T0
SPICLK
MOSI
MISO
SS
T1
T2
T2EX
CEX[4:0]
P89CV51RB2/RC2/RD2

P89CV51RD2FA,512

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
IC MCU 8BIT 64KB FLASH 44PLCC
Lifecycle:
New from this manufacturer.
Delivery:
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