P89CV51RB2_RC2_RD2_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 25 August 2009 66 of 76
NXP Semiconductors
P89CV51RB2/RC2/RD2
80C51 with 1 kB RAM, SPI
Fig 33. Shift register mode timing waveforms
002aaa552
ALE
0
instruction
1
2
3
4
5
6
7
8
01234567
valid valid valid valid valid valid valid valid
T
XLXL
set TI
set RI
t
XHQX
t
QVXH
t
XHDV
t
XHDX
clock
output data
write to SBUF
input data
clear RI
Table 58. SPI interface timing
Symbol Parameter Conditions Variable clock f
osc
=18MHz Unit
Min Max Min Max
f
SPI
SPI operating frequency 0 T
cy(clk)
/ 4 0 10 MHz
T
SPICYC
SPI cycle time see Figure 34, 35, 36, 37 4T
cy(clk)
- 222 - ns
t
SPILEAD
SPI enable lead time see Figure 36, 37 250 - 250 - ns
t
SPILAG
SPI enable lag time see Figure 36, 37 250 - 250 - ns
t
SPICLKH
SPICLK HIGH time see Figure 34, 35, 36, 37 2T
cy(clk)
- 111 - ns
t
SPICLKL
SPICLK LOW time see Figure 34, 35, 36, 37 2T
cy(clk)
- 111 - ns
t
SPIDSU
SPI data set-up time master or slave;
see
Figure 34, 35, 36, 37
100 - 100 - ns
t
SPIDH
SPI data hold time master or slave;
see
Figure 34, 35, 36, 37
100 - 100 - ns
t
SPIA
SPI access time see Figure 36, 37 0 80 0 80 ns
t
SPIDIS
SPI disable time see Figure 36, 37 0 160 - 160 ns
t
SPIDV
SPI enable to output data
valid time
see Figure 34, 35, 36, 37 - 111 - 111 ns
t
SPIOH
SPI output data hold time see Figure 34, 35, 36, 37 0-0-ns
t
SPIR
SPI rise time see Figure 34, 35, 36, 37
SPI outputs (SPICLK, MOSI,
MISO)
- 100 - 100 ns
SPI inputs (SPICLK, MOSI,
MISO,
SS)
- 2000 - 2000 ns
t
SPIF
SPI fall time see Figure 34, 35, 36, 37
SPI outputs (SPICLK, MOSI,
MISO)
- 100 - 100 ns
SPI inputs (SPICLK, MOSI,
MISO,
SS)
- 2000 - 2000 ns
