P89CV51RB2_RC2_RD2_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 25 August 2009 67 of 76
NXP Semiconductors
P89CV51RB2/RC2/RD2
80C51 with 1 kB RAM, SPI
Fig 34. SPI master timing (CPHA = 0)
T
SPICYC
t
SPICLKH
t
SPICLKH
t
SPICLKL
t
SPICLKL
master LSB/MSB outmaster MSB/LSB out
t
SPIDH
t
SPIDSU
t
SPIF
t
SPIOH
t
SPIDV
t
SPIR
t
SPIDV
t
SPIF
t
SPIR
t
SPIF
t
SPIR
SS
SPICLK
(CPOL = 0)
(output)
002aaa908
SPICLK
(CPOL = 1)
(output)
MISO
(input)
MOSI
(output)
LSB/MSB in
MSB/LSB in
Fig 35. SPI master timing (CPHA = 1)
T
SPICYC
t
SPICLKL
t
SPICLKL
t
SPICLKH
t
SPICLKH
master LSB/MSB outmaster MSB/LSB out
t
SPIDH
t
SPIDSU
t
SPIF
t
SPIOH
t
SPIDV
t
SPIR
t
SPIDV
t
SPIF
t
SPIF
t
SPIR
t
SPIR
SS
SPICLK
(CPOL = 0)
(output)
002aaa909
SPICLK
(CPOL = 1)
(output)
MISO
(input)
MOSI
(output)
LSB/MSB in
MSB/LSB in
P89CV51RB2_RC2_RD2_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 25 August 2009 68 of 76
NXP Semiconductors
P89CV51RB2/RC2/RD2
80C51 with 1 kB RAM, SPI
Fig 36. SPI slave timing (CPHA = 0)
T
SPICYC
t
SPICLKH
t
SPICLKH
t
SPICLKL
t
SPICLKL
t
SPILEAD
t
SPILAG
t
SPIDSU
t
SPIDH
t
SPIDH
t
SPIDSU
t
SPIDSU
t
SPIR
t
SPIA
t
SPIOH
t
SPIDIS
t
SPIR
slave MSB/LSB out
MSB/LSB in LSB/MSB in
slave LSB/MSB out
t
SPIDV
t
SPIOH
t
SPIOH
t
SPIDV
t
SPIR
t
SPIR
t
SPIF
t
SPIF
SS
SPICLK
(CPOL = 0)
(input)
002aaa910
SPICLK
(CPOL = 1)
(input)
MISO
(output)
MOSI
(input)
not defined
Fig 37. SPI slave timing (CPHA = 1)
002aaa911
T
SPICYC
t
SPICLKH
t
SPICLKH
t
SPICLKL
t
SPILEAD
t
SPICLKL
t
SPILAG
t
SPIDSU
t
SPIDSU
t
SPIDSU
t
SPIDH
t
SPIDH
t
SPIR
t
SPIR
t
SPIR
t
SPIA
t
SPIOH
t
SPIOH
t
SPIOH
t
SPIDIS
slave MSB/LSB out
not defined
MSB/LSB in LSB/MSB in
slave LSB/MSB out
t
SPIDV
t
SPIDV
t
SPIDV
t
SPIR
t
SPIF
t
SPIF
SS
SPICLK
(CPOL = 0)
(input)
SPICLK
(CPOL = 1)
(input)
MISO
(output)
MOSI
(input)
P89CV51RB2_RC2_RD2_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 25 August 2009 69 of 76
NXP Semiconductors
P89CV51RB2/RC2/RD2
80C51 with 1 kB RAM, SPI
Fig 38. Test load example
All other pins disconnected
Fig 39. I
DD
test condition, Active mode
All other pins disconnected
Fig 40. I
DD
test condition, Idle mode
002aaa555
to DUT
to tester
C
L
002aaa556
V
DD
V
DD
V
DD
P0
EARST
XTAL2
(n.c.)
clock
signal
XTAL1
V
SS
I
DD
V
DD
8
DUT
002aaa557
V
DD
V
DD
V
DD
P0
EARST
XTAL2
(n.c.)
clock
signal
XTAL1
V
SS
I
DD
8
DUT

P89CV51RD2FA,512

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
IC MCU 8BIT 64KB FLASH 44PLCC
Lifecycle:
New from this manufacturer.
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