P89CV51RB2_RC2_RD2_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 25 August 2009 44 of 76
NXP Semiconductors
P89CV51RB2/RC2/RD2
80C51 with 1 kB RAM, SPI
way to disable the WDT, except through a reset (either a hardware reset or a WDT
overflow reset). When the WDT overflows, it will drive an output reset HIGH pulse at the
RST pin.
When the WDT is enabled (and thus running) the user needs to reset it by writing 01EH
and 0E1H, in sequence, to the WDTRST SFR to avoid WDT overflow. The 14-bit counter
reaches overflow when it reaches 16383 (3FFFH) and this will reset the device.
The WDT’s counter cannot be read or written. When the WDT overflows it will generate an
output pulse at the RST pin with a duration of 98 oscillator periods in 6-clock mode or 196
oscillator periods in 12-clock mode.
6.9 PCA
The PCA includes a special 16-bit timer that has five 16-bit capture/compare modules
associated with it. Each of the modules can be programmed to operate in one of four
modes: rising and/or falling edge capture, software timer, high-speed output, or
pulse-width modulator. Each module has a pin associated with it: Module 0 is connected
to CEX0, module 1 to CEX1, etc. Registers CH and CL contain the current value of the
free-running up-counting 16-bit PCA timer. The PCA timer is a common time base for all
five modules and can be programmed to run at:
1
⁄
6
the oscillator frequency,
1
⁄
2
the
oscillator frequency, the Timer 0 overflow, or the input on the ECI pin (P1[2]). The timer
count source is determined from the CPS1 and CPS0 bits in the CMOD SFR; see
Table 32 and Table 33.
In the CMOD SFR there are three additional bits associated with the PCA. They are CIDL
which allows the PCA to stop during Idle mode, WDTE which enables or disables the
watchdog function on module 4, and ECF which when set causes an interrupt and the
PCA overflow flag CF (in the CCON SFR) to be set when the PCA timer overflows.
The watchdog timer function is implemented in module 4 of PCA.
The CCON SFR contains the run control bit for the PCA (CR) and the flags for the PCA
timer (CF) and each module (CCF[4:0]). To run the PCA the CR bit (CCON.6) must be set
by software. The PCA is shut off by clearing this bit. The CF bit (CCON.7) is set when the
PCA counter overflows and an interrupt will be generated if the ECF bit in the CMOD
Fig 19. PCA
MODULE0
PCA TIMER/COUNTER
P1[3]/CEX0
MODULE1
P1[4]/CEX1
MODULE2
P1[5]/CEX2
MODULE3
P1[6]/CEX3
MODULE4
P1[7]/CEX4
time base for PCA modules
Module functions:
- 16-bit capture
- 16-bit timer
- 16-bit high speed output
- 8-bit PWM
- watchdog timer (module 4 only)
16 bits
16 bits
002aab913
