P89CV51RB2_RC2_RD2_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 25 August 2009 47 of 76
NXP Semiconductors
P89CV51RB2/RC2/RD2
80C51 with 1 kB RAM, SPI
0 1 1 internal clock, f
osc
/6
1 0 2 Timer 0 overflow
1 1 3 external clock at pin P1[2]/ECI (maximum rate = f
osc
/4)
Table 35. CCON - PCA counter control register (address D8H) bit allocation
Bit addressable; reset value: 00H.
Bit 7 6 5 4 3 2 1 0
Symbol CF CR - CCF4 CCF3 CCF2 CCF1 CCF0
Table 36. CCON - PCA counter control register (address D8H) bit description
Bit Symbol Description
7 CF PCA Counter overflow Flag. Set by hardware when the counter rolls
over. CF flags an interrupt if bit ECF in CMOD is set. CF may be set by
either hardware or software but can only be cleared by software.
6 CR PCA Counter Run control. Set by software to turn the PCA counter on.
Must be cleared by software to turn the PCA counter off.
5 - Reserved for future use. Should be set to 0 by user programs.
4 CCF4 PCA Module 4 interrupt Flag. Set by hardware when a match or
capture occurs. Must be cleared by software.
3 CCF3 PCA Module 3 interrupt Flag. Set by hardware when a match or
capture occurs. Must be cleared by software.
2 CCF2 PCA Module 2 interrupt Flag. Set by hardware when a match or
capture occurs. Must be cleared by software.
1 CCF1 PCA Module 1 interrupt Flag. Set by hardware when a match or
capture occurs. Must be cleared by software.
0 CCF0 PCA Module 0 interrupt Flag. Set by hardware when a match or
capture occurs. Must be cleared by software.
Table 37. CCAPMn - PCA modules compare/capture register (address CCAPM0 DAH,
CCAPM1 DBH, CCAPM2 DCH, CCAPM3 DDH, CCAPM4 DEH) bit allocation
Not bit addressable; reset value: 00H.
Bit 7 6 5 4 3 2 1 0
Symbol - ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn
Table 38. CCAPMn - PCA modules compare/capture register (address CCAPM0 DAH,
CCAPM1 DBH, CCAPM2 DCH, CCAPM3 DDH, CCAPM4 DEH) bit description
Bit Symbol Description
7 - Reserved for future use. Should be set to 0 by user programs.
6 ECOMn Enable Comparator. ECOMn = 1 enables the comparator function.
5 CAPPn Capture Positive, CAPPn = 1 enables positive edge capture.
4 CAPNn Capture Negative, CAPNn = 1 enables negative edge capture.
3 MATn Match. When MATn = 1 a match of the PCA counter with this module’s
compare/capture register causes the CCFn bit in CCON to be set,
flagging an interrupt.
Table 34. CMOD - PCA counter mode register (address D9H) count pulse select
…continued
CPS1 CPS0 Select PCA input
