P89CV51RB2_RC2_RD2_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 25 August 2009 14 of 76
NXP Semiconductors
P89CV51RB2/RC2/RD2
80C51 with 1 kB RAM, SPI
The DPTR points to location 0A0H and the data in the accumulator is written to address
0A0H of the expanded RAM rather than off-chip external memory. Access to EXTRAM
addresses that are not present on the device (above 2FFH) will access external off-chip
memory and will perform in the same way as the standard 8051, with P0 and P2 as
data/address bus, and P3[6] and P3[7] as write and read timing signals.
When EXTRAM = 1, MOVX @Ri and MOVX @DPTR will be similar to the standard 8051.
Using MOVX @Ri provides an 8-bit address with multiplexed data on Port 0. Other output
port pins can be used to output higher order address bits. This provides external paging
capabilities. Using MOVX @DPTR generates a 16-bit address. This allows external
addressing up to 64 kB. Port 2 provides the high-order eight address bits (DPH), and
Port 0 multiplexes the low-order eight address bits (DPL) with data. Both MOVX @Ri and
MOVX @DPTR generates the necessary read and write signals (P3[6] - WR and P3[7] -
RD) for external memory use. Table 7 shows external data memory RD, WR operation
with EXTRAM bit.
The stack pointer (SP) can be located anywhere within the 256 B of internal RAM (lower
128 B and upper 128 B). The stack pointer may not be located in any part of the expanded
RAM.
Table 6. AUXR - Auxiliary function register (address 8EH) bit description
Bit Symbol Description
7 to 2 - Reserved for future use. Should be set to 0 by user programs.
1 EXTRAM Internal/external RAM access using MOVX @Ri/@DPTR. When 0,
accesses internal XRAM with address specified in MOVX instruction.
If address supplied with this instruction exceeds on-chip available
XRAM, off-chip RAM is accessed. When 1, every MOVX instruction
targets external data memory by default.
0 AO ALE off: disables/enables ALE. AO = 0 results in ALE emitted at a
constant rate of
1
⁄
2
the oscillator frequency. In case of AO = 1, ALE is
active only during a MOVX or MOVC.
Table 7. External data memory RD, WR with EXTRAM bit
AUXR MOVX @DPTR, A or MOVX A, @DPTR MOVX @Ri, A or MOVX A, @Ri
ADDR < 0300H ADDR ≥ 0300H ADDR = any
EXTRAM = 1
RD/WR asserted RD/WR asserted RD/WR asserted
EXTRAM = 0
RD/WR not asserted RD/WR asserted RD/WR not asserted
