P89CV51RB2_RC2_RD2_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 25 August 2009 28 of 76
NXP Semiconductors
P89CV51RB2/RC2/RD2
80C51 with 1 kB RAM, SPI
6.4.1 Mode 0
Putting either timer into Mode 0 makes it look like an 8048 timer, which is an 8-bit counter
with a fixed divide-by-32 prescaler. Figure 7 shows Mode 0 operation.
In this mode, the timer register is configured as a 13-bit register. As the count rolls over
from all 1s to all 0s, it sets the timer interrupt flag TFn. The count input is enabled to the
timer when TRn = 1 and either GATE = 0 or INTn = 1. (Setting GATE = 1 allows the timer
to be controlled by external input INTn, to facilitate pulse width measurements). TRn is a
control bit in the special function register TCON (Table 17). The GATE bit is in the TMOD
register.
The 13-bit register consists of all 8 bits of THn and the lower 5 bits of TLn. The upper
3 bits of TLn are indeterminate and should be ignored. Setting the run flag (TRn) does not
clear the registers.
Mode 0 operation is the same for Timer 0 and Timer 1; see Figure 7. There are two
different GATE bits, one for Timer 1 (TMOD.7) and one for Timer 0 (TMOD.3).
Table 17. TCON - Timer/Counter control register (address 88H) bit description
Bit Symbol Description
7 TF1 Timer 1 overflow Flag. Set by hardware on timer/counter overflow. Cleared
by hardware when the processor vectors to Timer 1 interrupt routine, or by
software.
6 TR1 Timer 1 Run control bit. Set/cleared by software to turn timer/counter 1
on/off.
5 TF0 Timer 0 overflow Flag. Set by hardware on timer/counter overflow. Cleared
by hardware when the processor vectors to Timer 0 interrupt routine, or by
software.
4 TR0 Timer 0 Run control bit. Set/cleared by software to turn timer/counter 0
on/off.
3 IE1 Interrupt 1 Edge flag. Set by hardware when external interrupt 1
edge/LOW-state is detected. Cleared by hardware when the interrupt is
processed, or by software.
2 IT1 Interrupt 1 Type control bit. Set/cleared by software to specify falling
edge/LOW-state that triggers external interrupt 1.
1 IE0 Interrupt 0 Edge flag. Set by hardware when external interrupt 0
edge/LOW-state is detected. Cleared by hardware when the interrupt is
processed, or by software.
0 IT0 Interrupt 0 Type control bit. Set/cleared by software to specify falling
edge/LOW-state that triggers external interrupt 0.
Fig 7. Timer/counter 0 or 1 in Mode 0 (13-bit counter)
002aaa519
osc/6
Tn pin
TRn
TnGate
INTn pin
C/T = 0
C/T = 1
TLn
(5-bits)
THn
(8-bits)
TFn
control
overflow
interrupt
