P89CV51RB2_RC2_RD2_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 25 August 2009 25 of 76
NXP Semiconductors
P89CV51RB2/RC2/RD2
80C51 with 1 kB RAM, SPI
Erase 8 kB/16 kB code block Input parameters:
R1 = 01H or 81H (WDT feed)
DPH = 00H, block 0, 0 kB to 8 kB
DPH = 20H, block 1, 8 kB to 16 kB
DPH = 40H, block 2, 16 kB to 32 kB
DPH = 80H, block 3, 32 kB to 48 kB
DPH = C0H, block 4, 48 kB to 64 kB
Return parameter(s):
ACC = 00: pass
ACC is not 00: fail
Program user code Input parameters:
R1 = 02H or 82H (WDT feed)
DPH = memory address MSB
DPL = memory address LSB
ACC = byte to program
Return parameter(s):
ACC = 00: pass
ACC is not 00: fail
Read user code Input parameters:
R1 = 03H or 83H (WDT feed)
DPH = memory address MSB
DPL = memory address LSB
Return parameter(s):
ACC = device data
Erase status bit and boot vector Input parameters:
R1 = 04H or 84H (WDT feed)
DPL = don’t care
DPH = don’t care
Return parameter(s):
ACC = 00: pass
ACC is not 00: fail
Program security bits Input parameters:
R1 = 05H or 85H (WDT feed)
DPL = 00H = security bit 1
DPL = 01H = security bit 2
DPL = 02H = security bit 3
Return parameter(s):
ACC = 00: pass
ACC is not 00: fail
Table 12. IAP function calls
…continued
IAP function IAP call parameters
P89CV51RB2_RC2_RD2_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 25 August 2009 26 of 76
NXP Semiconductors
P89CV51RB2/RC2/RD2
80C51 with 1 kB RAM, SPI
6.4 Timers/counters 0 and 1
The two 16-bit timer/counter registers: Timer 0 and Timer 1 can be configured to operate
either as timers or event counters (see Table 13 and Table 14).
In the ‘Timer’ function, the register is incremented every machine cycle. Thus, one can
think of it as counting machine cycles. Since a machine cycle consists of six oscillator
periods, the count rate is
1
6
of the oscillator frequency.
In the ‘Counter’ function, the register is incremented in response to a 1-to-0 transition at its
corresponding external input pin, T0 or T1. In this function, the external input is sampled
once every machine cycle.
When the samples show a HIGH in one cycle and a LOW in the next cycle, the count is
incremented. The new count value appears in the register in the machine cycle following
the one in which the transition was detected. Since it takes two machine cycles
(12 oscillator periods) for a 1-to-0 transition to be recognized, the maximum count rate is
1
12
of the oscillator frequency. There are no restrictions on the duty cycle of the external
input signal, but to ensure that a given level is sampled at least once before it changes, it
should be held for at least one full machine cycle. In addition to the ‘Timer’ or ‘Counter’
selection, Timer 0 and Timer 1 have four selectable operating modes.
Program status bit, boot vector,
6×/12× bit
Input parameters:
R1 = 06H or 86H (WDT feed)
DPL = 00H = program status bit
DPL = 01H = program boot vector
DPL = 02H = 6×/12× bit
ACC = boot vector value to program
Return parameter(s):
ACC = 00: pass
ACC is not 00: fail
Read security bits, status bit, boot
vector
Input parameters:
ACC = 07H or 87H (WDT feed)
DPL = 00H = security bits
DPL = 01H = status bit
DPL = 02H = boot vector
Return parameter(s):
ACC = 00 SoftICE S/N-match 0 SB 0 DBL_CLK
Erase page Input parameters:
R1 = 08H or 88H (WDT feed)
DPH = page address high byte
DPL = page address low byte
Return parameter(s):
ACC = 00: pass
ACC is not 00: fail
Table 12. IAP function calls
…continued
IAP function IAP call parameters
P89CV51RB2_RC2_RD2_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 25 August 2009 27 of 76
NXP Semiconductors
P89CV51RB2/RC2/RD2
80C51 with 1 kB RAM, SPI
The ‘Timer’ or ‘Counter’ function is selected by control bits C/T in the special function
register TMOD. These two timers/counters have four operating modes, which are selected
by bit-pairs (M1, M0) in TMOD. Modes 0, 1, and 2 are the same for both timers/counters.
Mode 3 is different. The four operating modes are described in the following text.
Table 13. TMOD - Timer/Counter mode control register (address 89H) bit allocation
Not bit addressable; reset value: 0000 0000B; reset source(s): any source.
Bit 7 6 5 4 3 2 1 0
Symbol T1GATE T1C/
T T1M1 T1M0 T0GATE T0C/T T0M1 T0M0
Table 14. TMOD - Timer/Counter mode control register (address 89H) bit description
Bit Symbol Description
7 T1GATE Gating control for Timer 1. When set, timer/counter is enabled only while
the
INT1 pin is HIGH and the TR1 control bit is set. When cleared, Timer 1
is enabled when the TR1 control bit is set.
6 T1C/
T Timer or counter select for Timer 1. Cleared for timer operation. Set for
counter operation (input from T1 input pin).
5 T1M1 Mode select for Timer 1.
4 T1M0
3 T0GATE Gating control for Timer 0. When set, timer/counter is enabled only while
the
INT0 pin is HIGH and the TR0 control bit is set. When cleared, Timer 0
is enabled when the TR0 control bit is set.
2 T0C/
T Timer or counter select for Timer 0. Cleared for timer operation. Set for
counter operation (input from T0 input pin).
1 T0M1 Mode select for Timer 0.
0 T0M0
Table 15. TMOD - Timer/Counter mode control register (address 89H) M1/M0 operating
mode
M1 M0 Operating mode
0 0 0 8048 timer ‘TLx’ serves as 5-bit prescaler.
0 1 1 16-bit timer/counter ‘THx’ and ‘TLx' are cascaded;
there is no prescaler.
1 0 2 8-bit auto-reload timer/counter ‘THx’ holds a value
which is to be reloaded into ‘TLx’ each time it overflows.
1 1 3 (Timer 0) TL0 is an 8-bit timer/counter controlled by the
standard Timer 0 control bits. TH0 is an 8-bit timer only
controlled by Timer 1 control bits.
1 1 3 (Timer 1) timer/counter 1 stopped.
Table 16. TCON - Timer/Counter control register (address 88H) bit allocation
Bit addressable; reset value: 0000 0000B; reset source(s): any reset.
Bit 7 6 5 4 3 2 1 0
Symbol TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

P89CV51RD2FA,512

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NXP Semiconductors
Description:
IC MCU 8BIT 64KB FLASH 44PLCC
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