P89CV51RB2_RC2_RD2_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 25 August 2009 41 of 76
NXP Semiconductors
P89CV51RB2/RC2/RD2
80C51 with 1 kB RAM, SPI
address of all don’t cares. This effectively disables the automatic addressing mode and
allows the microcontroller to use standard UART drivers which do not make use of this
feature.
6.7 Serial Peripheral Interface (SPI)
6.7.1 SPI features
• Master or slave operation
• 10 MHz bit frequency (max)
• LSB first or MSB first data transfer
• Four programmable bit rates
• End of transmission (SPIF)
• Write-collision flag protection (WCOL)
• Wake-up from Idle mode (Slave mode only)
6.7.2 SPI description
The serial peripheral interface allows high-speed synchronous data transfer between the
P89CV51RB2/RC2/RD2 and peripheral devices or between several
P89CV51RB2/RC2/RD2 devices. Figure 16 shows the correspondence between master
and slave SPI devices. The SPICLK pin is the clock output and input for the Master and
Slave modes, respectively. The SPI clock generator will start following a write to the
master devices SPI data register. The written data is then shifted out of the MOSI pin of
the master device into the MOSI pin of the slave device. Following a complete
transmission of one byte of data, the SPI clock generator is stopped and the SPI interrupt
Flag (SPIF) is set. An SPI interrupt request will be generated if the SPI Interrupt Enable bit
(SPIE) and the SPI interrupt enable bit, ES, are both set.
An external master drives the Slave Select input pin (SS) LOW to select the SPI module
as a slave. If SS has not been driven LOW, then the slave SPI unit is not active and the
MOSI pin can also be used as an input port pin.
CPHA and CPOL control the phase and polarity of the SPI clock (SCK). Figure 17 and
Figure 18 show the four possible combinations of these two bits.
