P89CV51RB2_RC2_RD2_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 25 August 2009 56 of 76
NXP Semiconductors
P89CV51RB2/RC2/RD2
80C51 with 1 kB RAM, SPI
6.12 Power-saving modes
The device provides two power-saving modes of operation for applications where power
consumption is critical. The two modes are Idle and Power-down; see Table 48.
6.12.1 Idle mode
Idle mode is entered by setting the IDL bit in the PCON register. In Idle mode, the program
counter is stopped. The system clock continues to run and all interrupts and peripherals
remain active. The on-chip RAM and the special function registers hold their data during
this mode.
The device exits Idle mode through either a system interrupt or a hardware reset. When
exiting Idle mode via system interrupt, the start of the interrupt clears the IDL bit and exits
Idle mode. After exiting the Interrupt Service Routine (ISR), the interrupted program
resumes execution at the instruction immediately following the instruction which invoked
the Idle mode. A hardware reset starts the device similar to a power-on reset.
6.12.2 Power-down mode
The Power-down mode is entered by setting the PD bit in the PCON register. In the
Power-down mode, the clock is stopped and external interrupts are active for
level-sensitive interrupts only. SRAM contents are retained during power-down, the
minimum V
DD
level is 4.5 V.
The device exits Power-down mode through either an enabled external level-sensitive
interrupt or a hardware reset. The start of the interrupt clears the PD bit and exits
power-down. Holding an external interrupt pin LOW restarts the oscillator, the signal must
hold LOW at least 1024 clock cycles before bringing back HIGH to complete the exit.
When the interrupt signal is restored to logic V
IH
, the interrupt service routine program
execution resumes at the instruction immediately following the instruction which invoked
Power-down mode. A hardware reset starts the device similar to a power-on reset.
To exit properly out of power-down, the reset or external interrupt should not be executed
before the V
DD
line is restored to its normal operating voltage. Be sure to hold V
DD
voltage
long enough at its normal operating level for the oscillator to restart and stabilize (normally
less than 10 ms).
Table 48. Power-saving modes
Mode Initiated by State of MCU Exited by
Idle Software (Set IDL bit
in PCON)
MOV PCON, #01H
CLK is running. Interrupts, serial
port and timers/counters are
active. Program counter is
stopped. ALE and
PSEN signals
at a HIGH-state during Idle. All
registers remain unchanged.
Enabled interrupt or hardware reset. Start of
interrupt clears IDL bit and exits Idle mode, after
the ISR RETI instruction, program resumes
execution beginning at the instruction following the
one that invoked Idle mode. A hardware reset
restarts the device similar to a power-on reset.
Power-down Software (Set PD bit
in PCON)
MOV PCON, #02H
CLK is stopped. On-chip SRAM
and SFR data is maintained.
ALE and
PSEN signals at a
LOW-state during power-down.
External interrupts are only
active for level-sensitive
interrupts, if enabled.
Enabled external level-sensitive interrupt or
hardware reset. Start of interrupt clears PD bit and
exits Power-down mode, after the ISR RETI
instruction program resumes execution beginning
at the instruction following the one that invoked
Power-down mode. A hardware reset restarts the
device similar to a power-on reset.
