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Test Conditions
DBVDD = 3.3V, DCVDD = 1.42 to 3.6V, DGND = 0V, T
A
= +25
o
C, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless
otherwise stated.
PARAMETER SYMBOL MIN TYP MAX UNIT
Program Register Input Information
SCLK Frequency
0 400 kHz
SCLK Low Pulse-Width
t
1
1.3 us
SCLK High Pulse-Width
t
2
600 ns
Hold Time (Start Condition)
t
3
600 ns
Setup Time (Start Condition)
t
4
600 ns
Data Setup Time
t
5
100 ns
SDIN, SCLK Rise Time
t
6
300 ns
SDIN, SCLK Fall Time
t
7
300 ns
Setup Time (Stop Condition)
t
8
600 ns
Data Hold Time
t
9
900 ns
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DEVICE DESCRIPTION
INTRODUCTION
The WM8737L is a low power analogue to digital converter (ADC) designed for audio recording. Its
features, performance and low power consumption make it ideal for recordable CD players, MP3
players, portable MD players and PDAs.
The device includes three stereo analogue inputs with a multiplexer to select between inputs. Each
input can be used as either a line level input or as a microphone input with on-chip microphone pre-
amplifiers. A programmable gain amplifier provides additional gain or attenuation, and can be used for
automatic level control (ALC), keeping the recording volume constant. It is also possible to use the
WM8737L as a mono device, or to mix the two channels to mono, either in the analogue or in the
digital domain.
The ADC is of a high quality using a multi-bit high-order oversampling architecture delivering high
SNR at low power consumption. It can operate at oversampling rates of 64fs (low power mode) or
128fs (normal power mode), allowing users to design for low power consumption or high
performance. The ADC also includes a digital high pass filter to remove unwanted DC components
from the audio signal. This filter may be turned off for DC measurements.
The output from the ADC is available on a configurable digital audio interface. It supports a number of
audio data formats including I
2
S, DSP Mode, Left justified and Right justified, and can operate in
master or slave modes.
The WM8737L master clock can be either an industry standard 256/384 f
s
clock or a 12MHz/24MHz
USB clock. Sample rates of 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz, 88.2kHz and 96kHz
can be generated directly from the master clock, without an external PLL. The digital filters are
optimised for each sample rate.
The WM8737L can be controlled through a 2 wire or 3 wire MPU control interface. It is fully
compatible and an ideal partner for a range of industry standard microprocessors, controllers and
DSPs.
The design of the WM8737L has minimised power consumption without compromising performance.
It can operate at very low voltages, can power off parts of the circuitry under software control and
includes standby and power off modes.
INPUT SIGNAL PATH
The signal path consists of a multiplexer switch to select between three sets of analogue inputs,
followed by a microphone boost preamplifier with selectable gain settings of 13dB, 18dB, 28dB and
33dB.
The microphone preamplifier feeds into a PGA (programmable gain amplifier) via an external
capacitor which removes dc offsets that could otherwise produce zipper noise when the PGA gain
changes. Alternatively, for line input signals, the microphone preamplifier can be bypassed to reduce
power consumption and noise. The PGA gain can be controlled either by the user or by the on-chip
ALC function (see Automatic Level Control).
The output signal from each PGA (left and right) enters an ADC where it is digitised. The two
channels can also be mixed in the analogue domain and digitised in one ADC while the other ADC is
switched off to reduce power consumption (see “Power Management” section). The mono-mix signal
appears on both digital output channels.
LEFT AND RIGHT CHANNEL SIGNAL INPUTS
The WM8737L has two sets of low capacitance ac coupled analogue inputs, LINPUT1, LINPUT2,
LINPUT3 and RINPUT1, RINPUT2, RINPUT3. The LINSEL and RINSEL control bits select between
them. These inputs can be configured as microphone or line inputs by enabling or disabling the
microphone preamplifier. All inputs have high impedance when the preamplifier is used and their
impedance is between 1.8k and 50k (depending on PGA gain) if the preamplifier is bypassed.
The microphone preamplifier has very high gain settings. Care should be taken to prevent the input
signal to the microphone preamplifier from exceeding the supply rails which will saturate the
microphone preamplifier and may cause the preamplifier to oscillate. This is more likely to happen at
the higher gain settings of +28dB and +33dB. The input signal should be limited to prevent the input
signal from exceeding the supply rails and saturating the microphone preamplifier.
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The signal inputs are internally high-impedance biased to the reference voltage, VREF. Whenever
line inputs are muted or the device is placed into standby mode 2 (see “Power Management” section),
the inputs stay biased to VREF. This reduces any audible clicks that may otherwise be heard when
changing inputs or awakening from standby.
DC MEASUREMENT
For dc measurements (battery voltage monitoring for example), the LINPUT1 and/or RINPUT1 pins
can be taken directly into the respective ADC, bypassing the microphone preamplifier and PGA.
In dc mode the ADC output is mid-scale for L/RINPUT1 voltage AGND and full-scale for L/RINPUT
voltage 1.7 x AVDD. Note that L/RINPUT1 must not exceed AVDD and so a voltage divider will be
required to bring the battery voltage into range.
REGISTER
ADDRESS
BIT LABEL DEFAULT DESCRIPTION
R2 (02h)
Analogue Audio
Path Control
(Left Channel)
8:7
LINSEL 00 Left Channel Input Select
00: LINPUT1
01: LINPUT2
10: LINPUT3
11: dc measure on LINPUT1
6:5
LMICBOOST[1:0] 00 Left Channel Microphone Gain Boost
00: 13dB boost
01: 18dB boost
10: 28dB boost
11: 33dB boost
4
LMBE 0 Left Channel Mic Boost Enable
0: Mic preamp disabled, bypass switch
is closed.
1: Mic preamp is enabled, bypass
switch is open.
R3 (03h)
Analogue Audio
Path Control
(Right Channel)
8:7
RINSEL 00 Right Channel Input Select
00: RINPUT1
01: RINPUT2
10: RINPUT3
11: dc measure on RINPUT1
6:5
RMICBOOST[1:0] 00 Right Channel Microphone Gain Boost
Same as LMICBOOST
4
RMBE 0 Right Channel Mic Boost Enable
Same as LMBE
Table 2 Input Software Control
The internal VREF input bias may cause unwanted loading of any potential divider connected to
L/RINPUT1 for the purpose of dc measurement. In this case, the internal bias sources can be
disabled by setting the appropriate bits of register R10 to zero.
REGISTER
ADDRESS
BIT LABEL DEFAULT DESCRIPTION
R10 (0Ah)
DC Measure
Control
0
RINPUT1 dc BIAS
ENABLE
1 0: Disable dc bias to RINPUT1
1: Enable dc bias to RINPUT1
1
LINPUT1 dc BIAS
ENABLE
1 0: Disable dc bias to LINPUT1
1: Enable dc bias to LINPUT1
Table 3 DC Measurement Bias Control

WM8737CLGEFL/R

Mfr. #:
Manufacturer:
Cirrus Logic
Description:
Audio A/D Converter ICs Stereo ADC Low Power
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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