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WM8737CLGEFL/R

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WM8737L Production Data
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PD, Rev 4.4, January 2012
28
REGISTER
ADDRESS
BIT LABEL DEFAULT DESCRIPTION
4 LRP 0 Right, left & I2S modes – ADCLRC
polarity
1 = invert ADCLRC polarity
0 = normal ADCLRC polarity
DSP Mode – mode A/B select
1 = MSB is available on 1st BCLK
rising edge after ADCLRC rising edge
(mode B)
0 = MSB is available on 2nd BCLK
rising edge after ADCLRC rising edge
(mode A)
6 MS 0 Master / Slave Mode Control
1: Master Mode
0: Slave Mode
7 SDODIS 0 ADCDAT serial data pin disable
0: ADCDAT pin enabled
1: ADCDAT pin off (high impedance)
Table 14 Audio Data Format Control
Note: Right Justified mode does not support 32-bit data. If WL=11 in Right justified mode, the actual
word length is 24 bits.
To prevent any communication problems on the Audio Interface, the interface is disabled (ADCDAT
tristated and floating) when the WM8737L starts up. Once the Audio Interface and sample rates have
been programmed, the audio interface can be activated under software control by setting the AI bit
(see “Power Management” section).
MASTER CLOCK AND AUDIO SAMPLE RATES
The master clock (MCLK) is used to operate the digital filters and the noise shaping circuits. The
WM8737L supports a wide range of master clock frequencies, and can generate many commonly
used audio sample rates directly from the master clock.
There are two clocking modes:
‘Normal’ mode supports master clocks of 128f
s
, 192f
s
, 256f
s
, 384f
s
, and their multiples
USB mode supports 12MHz or 24MHz master clocks. This mode is intended for use in
systems with a USB interface, and eliminates the need for an external PLL to generate
another clock frequency for the audio ADC.
REGISTER
ADDRESS
BIT LABEL DEFAULT DESCRIPTION
R8 (08h)
Clocking and
Sample Rate
Control
6 CLKDIV2 0 Master Clock Divide by 2
1: MCLK is divided by 2
0: MCLK is not divided
0 USB 0 Clocking Mode Select
1: USB Mode
0: ‘Normal’ Mode
5:1 SR[4:0] 0000 Sample Rate Control
7 AUTO
DETECT
0 Clock Ratio Autodetect
(Slave Mode Only)
0: Autodetect Off
1: Autodetect On
Table 15 Clocking and Sample Rate Control
Production Data WM8737L
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The clocking of the WM8737L is controlled using the CLKDIV2, USB, and SR control bits. Setting the
CLKDIV2 bit divides MCLK by two internally. The USB bit selects between ‘Normal’ and USB mode.
Each combination of the SR4 to SR0 control bits selects one sample rate (see next page). The digital
filter characteristics are automatically adjusted to suit the MCLK and sample rate selected (see Digital
Filter Characteristics).
Since all sample rates are generated by dividing MCLK, their accuracy depends on the accuracy of
MCLK. If MCLK changes, the sample rates change proportionately. Note that some sample rates (e.g.
44.1kHz in USB mode) are approximated, i.e. they differ from their target value by a very small
amount. This is not audible, as the maximum deviation is only 0.27% (48.0214kHz instead of 48kHz
in USB mode - for comparison, a half-tone step corresponds to a 5.9% change in pitch).
In slave mode, it is possible to autodetect the audio clock rate ratio, instead of programming it. The
WM8737L can autodetect the following clock ratios:
CLKDIV2 = 0: MCLK = 128f
s
, 192f
s
, 256f
s
, or 384f
s
subject to MCLK < 40MHz
CLKDIV2 = 1: MCLK = 256f
s
, 384f
s
, 512f
s
, 768f
s
, 1024f
s
, 1536f
s
, subject to MCLK <
40MHz
MCLK
CLKDIV2=0
MCLK
CLKDIV2=1
ADC SAMPLE RATE USB SR [4:0] FILTER
TYPE
Normal Clock Mode
12.288MHz 24.576MHz 16 kHz (MCLK/768) 0 01010 A
24 kHz (MCLK/512) 0 11100 A
32 kHz (MCLK/384) 0 01100 A
48 kHz (MCLK/256) 0 00000 A
96 kHz (MCLK/128) (see Note 1) 0 01110 B
11.2896MHz
22.5792MHz
22.05 kHz (MCLK/512) 0 11010 A
44.1 kHz (MCLK/256) 0 10000 A
88.2 kHz (MCLK/128) (see Note 1) 0 11110 B
18.432MHz
36.864MHz
16 kHz (MCLK/1152) 0 01011 A
24 kHz (MCLK/768) 0 11101 A
32 kHz (MCLK/576) 0 01101 A
48 kHz (MCLK/384) 0 00001 A
96 kHz (MCLK/192) (see Note 1) 0 01111 B
16.9344MHz
33.8688MHz
22.05 kHz (MCLK/768) 0 11011 A
44.1 kHz (MCLK/384) 0 10001 A
88.2 kHz (MCLK/192) (see Note 1) 0 11111 B
USB Mode
12.000MHz 24.000MHz 16 kHz (MCLK/750) 1 01010 C
22.0588 kHz (MCLK/544) 1 11011 A
24 kHz (MCLK/500) 1 11100 C
32 kHz (MCLK/375) 1 01100 C
44.118 kHz (MCLK/272) 1 10001 A
48 kHz (MCLK/250) 1 00000 C
88.235 kHz (MCLK/136) (see Note 1) 1 11111 B
96 kHz (MCLK/125) 1 01110 D
Table 16 Master Clock and Sample Rates
Note 1: The 3D enhancement is not supported at sample frequencies of 88.2kHz, 88.235kHz,
and 96kHz. When using these sample frequencies the 3D enhancement function
should be bypassed by first setting register R13 (0Dh) to 1_110x_xxxx (1C0h), where
x_xxxx represents the required values for the ALC in the application, and then setting
register R28 (1Ch) to 0_0000_0100 (004h).
Note that the above sequence uses test bits that are not documented and the use of
these test bits, other than as described above, is not recommended and is not
supported.
WM8737L Production Data
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30
CONTROL INTERFACE
SELECTION OF CONTROL MODE
The WM8737L is controlled by writing to registers through a serial control interface. A control word
consists of 16 bits. The first 7 bits (B15 to B9) are address bits that select which control register is
accessed. The remaining 9 bits (B8 to B0) are register bits, corresponding to the 9 bits in each control
register. The control interface can operate as either a 3-wire or 2-wire MPU interface. The MODE pin
selects the interface format.
MODE INTERFACE FORMAT
Low 2 wire
High 3 wire
Table 17 Control Interface Mode Selection
3-WIRE SERIAL CONTROL MODE
In 3-wire mode, every rising edge of SCLK clocks in one data bit from the SDIN pin. A rising edge on
CSB latches in a complete control word consisting of the last 16 bits.
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
SDIN
SCLK
CSB
control register address control register data bits
latch
Figure 17 3-Wire Serial Control Interface
2-WIRE SERIAL CONTROL MODE
The WM8737L supports software control via a 2-wire serial bus. Many devices can be controlled by
the same bus, and each device can be identified by one of two 7-bit address (this is not the same as
the 7-bit address of each register in the WM8737L).
The WM8737L interface can be written to only and cannot be read back. The controller indicates the
start of data transfer with a high to low transition on SDIN while SCLK remains high. This indicates
that a device address and data will follow. All devices on the 2-wire bus respond to the start condition
and shift in the next eight bits on SDIN (7-bit address + Read/Write bit, MSB first). If the device
address received matches the address of the WM8737L and the R/W bit is ‘0’, indicating a write, then
the WM8737L responds by pulling SDIN low on the next clock pulse (ACK). If the address is not
recognised or the R/W bit is ‘1’, the WM8737L returns to the idle condition and wait for a new start
condition and valid address.
Once the WM8737L has acknowledged a correct address, the controller sends the first byte of control
data (B15 to B8, i.e. the WM8737L register address plus the first bit of register data). The WM8737L
then acknowledges the first data byte by pulling SDIN low for one clock pulse. The controller then
sends the second byte of control data (B7 to B0, i.e. the remaining 8 bits of register data), and the
WM8737L acknowledges again by pulling SDIN low.
The transfer of data is complete when there is a low to high transition on SDIN while SCLK is high.
After receiving a complete address and data sequence the WM8737L returns to the idle state and
waits for another start condition. If a start or stop condition is detected out of sequence at any point
during data transfer (i.e. SDIN changes while SCLK is high), the device jumps to the idle condition.
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WM8737CLGEFL/R

Mfr. #:
Buy WM8737CLGEFL/R
Manufacturer:
Cirrus Logic
Description:
Audio A/D Converter ICs Stereo ADC Low Power
Lifecycle:
New from this manufacturer.
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