Production Data WM8737L
w
PD, Rev 4.4, January 2012
7
Test Conditions
DCVDD = 1.5V, AVDD = MVDD = 3.3V, T
A
= +25
o
C, 1kHz -1dBFS signal, Normal Power Mode, fs = 48kHz, PGA gain = 0dB, 24-
bit audio data, unless otherwise stated.
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
Line Inputs (LINPUT1/2/3, RINPUT1/2/3) to ADC – MIC pre-amp BYPASSED
Full Scale Input Signal Level
(for ADC 0dB Input at 0dB Gain)
AVDD = 3.3V 1.0 V rms
AVDD = 1.8V 0.545
Signal to Noise Ratio
(A-weighted)
(Note 1)
SNR
AVDD = 3.3V,
Normal Power Mode
90 97 dB
AVDD = 2.7V,
Normal Power Mode
95
AVDD = 1.8V,
Normal Power Mode
92
AVDD = 3.3V,
Low Power Mode
95
AVDD = 2.7V,
Low Power Mode
93
AVDD = 1.8V,
Low Power Mode
90
Dynamic Range
(A-weighted)
(Note 2)
DNR
-60dBFS,
Normal Power Mode
90 97 dB
-60dBFS,
Low Power Mode
95
Total Harmonic Distortion
(Note 3)
THD
-1dB input -84 (0.006%) dB
%
-1dB input,
AVDD=1.8V
-81 (0.009%)
ADC Channel Separation
(Note 4)
1kHz signal 105 dB
Channel Matching
1kHz signal 0.2 dB
Programmable Gain Amplifier (PGA)
Programmable Gain
-97 0 30 dB
Programmable Gain Step Size
Monotonic 0.5 dB
Gain Error (Deviation from ideal
0.5dB/step gain characteristic)
1kHz signal -0.3 0.3 dB
Input Resistance
0dB gain 30 k
30dB gain 1.9
Input Capacitance
16.9pF pF
Automatic Level Control (ALC)
Typical Record Level
-18 -3 dB
Gain Hold Time (Note 5) t
HLD
MCLK = 12.288MHz
(Note 3)
0, 2.67, 5.33, 10.67, … , 43691
(time doubles with each step)
ms
Gain Ramp-Up (Decay) Time
(Notes 6, 7)
t
DCY
33.6, 67.2, 134.4, … , 3441
(time doubles with each step)
ms
Gain Ramp-Down (Attack) Time
(Notes 6, 7)
t
ATK
8.4, 16.8, 33.6, … , 8600
(time doubles with each step)
ms
WM8737L Production Data
w
PD, Rev 4.4, January 2012
8
Test Conditions
DCVDD = 1.5V, AVDD = MVDD = 3.3V, T
A
= +25
o
C, 1kHz -1dBFS signal, Normal Power Mode, fs = 48kHz, PGA gain = 0dB, 24-
bit audio data, unless otherwise stated.
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
Analogue Reference Levels
Mid-rail Reference Voltage VMID
–3% AVDD/2 +3% V
VMID Output Resistance R
VMID
75 k
Buffered Reference Voltage VREF
–3% AVDD/2 +3% V
Microphone Bias
Bias Voltage
V
MICBIAS
MICBIAS = 01 0.75AVDD V
MICBIAS = 10 0.9AVDD
–3%
0.9AVDD 0.9AVDD
+3%
V
MICBIAS = 11,
AVDD = 2.5V
1.2AVDD V
Bias Current Source
I
MICBIAS
3 mA
Output Noise Voltage
Vn 1K to 20kHz 24 nV/Hz
Digital Input / Output
Input HIGH Level
V
IH
0.7DBVDD V
Input LOW Level
V
IL
0.3DBVDD V
Output HIGH Level
V
OH
I
OH
= 1mA 0.9DBVDD V
Output LOW Level
V
OL
I
OL
= -1mA 0.1DBVDD V
TERMINOLOGY
1. Signal-to-noise ratio (dB) – for the microphone preamplifiers, quoted SNR is the ratio of the rms voltages of the full-
scale output at the L/RACOUT pins and the noise observed at these pins with no input signals. This figure indicates
only the microphone preamplifier noise and does not account for additional noise that will be added by the PGAs and
ADCs in obtaining the final digitised result. For the line inputs, quoted SNR is the ratio of the rms code ranges as
measured at the ADC output for a full-scale output signal and the noise observed with no input. This figure combines
the PGA and ADC noise contributions. (No Auto-zero or Auto-mute function is employed in achieving these results).
2. Dynamic range (dB) - DR measures the ratio in the ADC output between the full-scale signal power and all power
contributed by noise and spurious tones in the specified bandwidth. Normally THD+N is measured at 60dB below full
scale (to reduce any distortion components to negligible levels) and the measurement is then corrected by adding the
60dB to its magnitude. (e.g. THD+N @ -60dB= -32dB, DR= 60 + |-32| = 92dB).
3. Total Harmonic Distortion and Noise (dB) - THD+N is a ratio of the rms values of (Noise + Distortion) and Signal.
4. Channel Separation (dB) - Also known as Cross-Talk. This is a measure of the amount one channel is isolated from
the other. Normally measured by sending a full scale signal down one channel and measuring how much of this signal
appears at the output of the other channel.
5. Hold Time is the length of time between a signal detected by the ALC as being too quiet and beginning to ramp up the
gain. It does not apply to ramping down the gain when the signal is too loud, which happens without a delay.
6. Ramp-up and Ramp-Down times are defined as the time it takes for the PGA to sweep across 90% of its gain range.
7. All hold, ramp-up and ramp-down times scale proportionally with MCLK
Notes:
1. All performance measurements are done with a 20kHz low pass filter, and where noted an A-weight filter. Failure to
use such a filter will result in higher THD+N and lower SNR and Dynamic Range readings than are found in the
Electrical Characteristics. The low pass filter removes out of band noise; although this is not audible, it may affect
dynamic specification values.
2. VMID and VREF are each to be decoupled to a clean analogue ground with 10uF and 0.1uF capacitors placed as
close to the device package as possible. Smaller capacitors may reduce performance. VREFP should be connected to
VREF and VREFN should be connected to AGND using short PCB traces. It is not recommended to connect other
components to VMID or VREF in case of noise injection to the internal references of the device.
Production Data WM8737L
w
PD, Rev 4.4, January 2012
9
POWER CONSUMPTION
The power consumption of the WM8737L depends on the following factors.
Supply voltages: Reducing the supply voltages also reduces supply currents, and therefore results in significant power
savings (at the cost of reduced maximum SNR and THD performance).
Operating mode: Power consumption is lower when microphone pre-amps are not used. It can be also reduced in mono
or analogue mix-to-mono modes by switching off unused PGAs and ADCs via the power management register.
MODE DESCRIPTION POWER MANAGEMENT REGISTER
SETTING
TYP. SUPPLY CURRENTS
(MILLIAMPS)
TOTAL
POWER
(mW)
I
AVDD
I
DBVDD
I
DCVDD
MVDD = 1.8V, AVDD = 1.8V, DBVDD = 1.8V, DCVD = 1.5V, Low Power Mode, no MICBIAS or mic preamps
OFF 000000000
0.000 0.000 0.007 0.011
Standby 110000000
0.692 0.004 0.009 1.356
Mono (L/R) 111101000 / 111010100
1.978 0.011 1.633 6.029
Stereo / Digital Mono Mix 111111100
3.205 0.018 1.666 8.299
Analogue mono mix
(without dc monitoring via
Right ADC)
111111000
2.543 0.017 1.640 6.537
Analogue mono mix
(with continuous dc
monitoring via Right ADC)
111111100
3.205 0.018 1.670 8.306
Using MICBIAS in 0.9 X
AVDD mode in addition to
any of the above
Set appropriate MICBIAS[1:0] bits in
power management register
+0.255 - - +0.459
Using microphone boost
preamplifiers in addition to
any of the above
Set appropriate MBCTRL[1:0] bits in
register 09h and set LMBE and/or RMBE
bits in registers 02h and 03h
+0.692 - - +1.688
MVDD = 3.3V, AVDD = 3.3V, DBVDD = 3.3V, DCVDD = 1.5V, Low Power Mode, no MICBIAS or mic preamps
OFF 000000000
0.000 0.000 0.007 0.011
Standby 110000000
1.288 0.007 0.064 0.117
Mono (L/R) 111101000 / 111010100
2.993 0.018 1.624 12.173
Stereo / Digital Mono Mix 111111100
4.453 0.031 1.650 17.273
Analogue mono mix
(without dc monitoring via
Right ADC)
111111000
3.684 0.018 1.620 14.648
Analogue mono mix
(with continuous dc
monitoring via Right ADC)
111111100
4.453 0.031 1.660 17.288
Using MICBIAS in 0.9 X
AVDD mode in addition to
any of the above
Set appropriate MICBIAS[1:0] bits in
power management register
+0.47 - - +1.551
Using microphone boost
preamplifiers in addition to
any of the above
Set appropriate MBCTRL[1:0] bits in
register 09h and set LMBE and/or RMBE
bits in registers 02h and 03h
+1.413 - - +4.663

WM8737CLGEFL/R

Mfr. #:
Manufacturer:
Cirrus Logic
Description:
Audio A/D Converter ICs Stereo ADC Low Power
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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