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The ALC function is enabled using the ALCSEL[1:0] control bits in register R12. When enabled, the
recording volume can be programmed between -3dB and -18dB (relative to ADC full scale) using the
ALCL[3:0] register bits in register R12.
R13 and R14 bits HLD[3:0], DCY[3:0] and ATK[3:0] control the hold, decay and attack times,
respectively:
Hold time is the time delay between the peak level detected being below target and the PGA gain
beginning to ramp up. It can be programmed in power-of-two (2
n
) steps, e.g. 2.67ms, 5.33ms,
10.67ms etc. up to 43.7ms. Alternatively, the hold time can also be set to zero. The hold time only
applies to gain ramp-up, there is no delay before ramping the gain down when the signal level is
above target.
Decay time (Gain Ramp-Up) is the time that it takes for the PGA gain to ramp up across 90% of its
range (e.g. from –15dB up to 25.5 dB). The time it takes for the recording level to return to its target
value therefore depends on both the decay time and on the gain adjustment required. If the gain
adjustment is small, it will be shorter than the decay time. The decay time can be programmed in
power-of-two (2
n
) steps, from 33.6ms, 67.2ms, 134.4ms etc. to 34.41s.
Attack time (Gain Ramp-Down) is the time that it takes for the PGA gain to ramp down across 90% of
its range (e.g. from 25.5dB down to -15dB gain). The time it takes for the recording level to return to
its target value therefore depends on both the attack time and on the gain adjustment required. If the
gain adjustment is small, it will be shorter than the attack time. The attack time can be programmed in
power-of-two (2
n
) steps, from 8.4ms, 16.8ms, 33.6ms etc. to 8.6s.
When operating in stereo, the peak detector takes the maximum of left and right channel peak values,
and any new gain setting is applied to both left and right PGAs, so that the stereo image is preserved.
However, the ALC function can also be enabled on one channel only. In this case, only one PGA is
controlled by the ALC mechanism, while the other channel runs independently with its PGA gain set
through the control register.
When one ADC channel is unused or used for dc measurement, the peak detector disregards that
channel. The ALC function can operate in digital mono mix mode (MONOMIX = 10), but not in
analogue mono mix mode (MONOMIX = 01).
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REGISTER
ADDRESS
BIT LABEL DEFAULT DESCRIPTION
R12 (0Ch)
ALC Control 1
8:7 ALCSEL[1:0] 00 ALC function select
00 = ALC off (PGA gain set by
register)
01 = Right channel only
10 = Left channel only
11 = Stereo (PGA registers unused)
6:4 MAXGAIN 111 Set maximum gain for the PGA
111 : +30dB
110 : +24dB
…..(-6dB steps)
001 : -6dB
000 : -12dB
3:0 ALCL[3:0] 1100 ALC target level – sets signal level
after PGA at ADC input in 1dB steps
0000: -18dB FS
0001: -17dB FS
1110: -4dB FS
1111: -3dB FS
R13 (0Dh)
ALC Control 2
3:0 HLD[3:0] 0000 ALC hold time before gain is increased
0000: 0ms
0001: 2.67ms
0010: 5.33ms
… (time doubles with every step)
1111: 43.691s
4 ALCZCE 0 Enable zero-cross function for the ALC
gain updates
0: Zero-cross disabled
1: Zero-cross enabled
R14 (0Eh)
ALC Control 3
3:0 ATK[3:0] 0010 ALC attack (gain ramp-down) time
0000: 8.4ms
0001: 16.8ms
0010: 33.6ms
… (time doubles with every step)
1010 or higher = 8.6s
7:4 DCY[3:0] 0011 ALC decay (gain ramp-up) time
0000: 33.6ms
0001: 67.2ms
0010: 134.4ms
… (time doubles with every step)
1010 or higher = 34.41s
Table 12 ALC Control
PEAK LIMITER
To prevent clipping when a large signal occurs just after a period of quiet, the ALC circuit includes a
limiter function. If the ADC input signal exceeds 87.5% of full scale (–1.16dBFS), the PGA gain is
ramped down at the maximum attack rate (as when ATK = 0000), until the signal level falls below
87.5% of full scale. This function is automatically enabled whenever the ALC is enabled.
(Note: If ATK = 0000, then the limiter makes no difference to the operation of the ALC. It is designed
to prevent clipping when long attack times are used.)
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NOISE GATE
When the signal is very quiet and consists mainly of noise, the ALC function may cause “noise
pumping”, i.e. loud hissing noise during silence periods. The WM8737L has a noise gate function that
prevents noise pumping by comparing the signal level at the LINPUT1/2/3 and/or RINPUT1/2/3 pins
against a noise gate threshold, NGTH. The noise gate cuts in when:
Signal level at ADC [dB] < NGTH [dB] + PGA gain [dB] + Mic preamp gain [dB]
This is equivalent to:
Signal level at input pin [dB] < NGTH [dB]
When the noise gate is triggered, the PGA gain is held constant (preventing it from ramping up as it
would normally when the signal is quiet).
The table below summarises the noise gate control register. The NGTH control bits set the noise gate
threshold with respect to the ADC full-scale range. The threshold is adjusted in 6dB steps. Levels at
the extremes of the range may cause inappropriate operation, so care should be taken with set–up of
the function. Note that the noise gate only works in conjunction with the ALC function, and always
operates on the same channel(s) as the ALC (left, right, both, or none).
REGISTER
ADDRESS
BIT LABEL DEFAULT DESCRIPTION
R11 (0Bh)
Noise Gate
Control
0
NGAT 0 Noise gate function enable
1 = enable
0 = disable
4:2
NGTH[2:0] 000 Noise gate threshold (with respect to
ADC output level)
000: -78dBFS
001: -72dBfs
… 6 dB steps
110: -42dBFS
111: -30dBFS
Table 13 Noise Gate Control
DIGITAL AUDIO INTERFACE
The digital audio interface uses three pins:
ADCDAT: ADC data output
ADCLRC: ADC data alignment clock
BCLK: Bit clock, for synchronisation
The digital audio interface takes the data from the internal ADC digital filters and places it on
ADCDAT and ADCLRC. ADCDAT is the formatted digital audio data stream output from the ADC
digital filters with left and right channels multiplexed together. ADCLRC is an alignment clock that
indicates whether Left or Right channel data is present on the ADCDAT line. ADCDAT and ADCLRC
are synchronous with the BCLK signal with each data bit transition signified by a BCLK high to low
transition. ADCDAT is always an output. BCLK and ADCLRC may be inputs or outputs depending
whether the device is in master or slave mode (see Master and Slave Mode Operation, below).
Four different audio data formats are supported:
Left justified
Right justified
I
2
S
DSP mode
All four of these modes are MSB first. They are described in Audio Data Formats, below. Refer to the
Electrical Characteristic section for timing information.

WM8737CLGEFL/R

Mfr. #:
Manufacturer:
Cirrus Logic
Description:
Audio A/D Converter ICs Stereo ADC Low Power
Lifecycle:
New from this manufacturer.
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