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LTC6803HG-2#PBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P40
LTC6803-2/LTC6803-4
19
680324fa
OPERATION
Figure 4
XOR
BEGIN PEC[7:0] = 0x41
PEC Hardware and Software Example
BEGIN PEC[7:0] = 0x41
END
IN0
INO
IN0
PEC2
XOR
XOR
PEC[0]
PEC[1]
PEC1
PEC[7]
DATAIN
CLOCK
PEC[0]
CLK
DTFF
D Q
Q
PEC[1]
CLK
DTFF
D Q
Q
PEC[2]
CLK
DTFF
D Q
Q
1
INO = DATAIN XOR PEC[7];
1
INO = DATAIN XOR PEC[7];
2
PEC1 = PEC[0] XOR IN0;
2
PEC1 = PEC[0] XOR IN0;
3
PEC2 = PEC[1] XOR IN0;
3
PEC2 = PEC[1] XOR IN0;
4
PEC[7:0] = {PEC[6:2], PEC2, PEC1, IN0};
4
PEC[7:0] = {PEC[6:2], PEC2, PEC1, IN0};
PEC[2] PEC[3] PEC[4]
END
PEC[5] PEC[6]
PEC[7]
680324 F04
PEC[3]
CLK
DTFF
D Q
Q
PEC[4]
CLK
DTFF
D Q
Q
PEC[5]
CLK
DTFF
D Q
Q
PEC[6]
CLK
DTFF
D Q
Q
PEC[7]
CLK
DTFF
D Q
Q
LTC6803-2/LTC6803-4
20
680324fa
Toggle Polling: Toggle polling allows a robust determina-
tion both of device states and of the integrity of the con-
nections between the devices in a stack. Toggle polling is
enabled when the LVLPL bit is low. After entering a polling
command, the data out line will be driven by the slave
devices based on their status. When polling for the ADC
converter status, data out will be low when any device is
busy performing an ADC conversion and will toggle at
1kHz when no device is busy. Similarly, when polling for
interrupt status, the output will be low when any device
has an interrupt condition and will toggle at 1kHz when
none has an interrupt condition.
Toggle Polling—Address Polling: The addressed device
drives the SDO line based on its state alone—low for busy/
in interrupt, toggling at 1kHz for not busy/not in interrupt.
Toggle Polling—Parallel Broadcast Polling: No part ad-
dress is sent, so all devices respond simultaneously. If a
device is busy/in interrupt, it will pull SDO low. If a device
is not busy/not in interrupt, then it will release the SDO line
(TOS = 0) or attempt to toggle the SDO line at 1kHz (TOS
= 1).The master controller pulls CSBI high to exit polling.
CSBI
SCKI
SDI
SDO
MSB (CMD)
BIT6 (CMD) LSB (PEC)
TOGGLE OR LEVEL POLL
t
CYCLE
680324 F05
CSBI
SCKI
SDI
SDO
MSB (CMD)
BIT6 (CMD) LSB (PEC)
TOGGLE OR LEVEL POLL
680324 F06
Figure 5. Transmission Format (ADC Conversion and Poll)
Figure 6. Transmission Format (PLADC Conversion or PLINT)
Level Polling: Level polling is enabled when the LVLPL
bit is high. After entering a polling command, the data
out line will be driven by the slave devices based on their
status. When polling for the ADC converter status, data
out will be low when any device is busy performing an
ADC conversion and will be high when no device is busy.
Similarly, when polling for interrupt status, the output will
be low when any device has an interrupt condition and will
be high when none has an interrupt condition.
Level Polling—Address Polling: The addressed device
drives the SDO line based on its state alone—pulled low
for busy/in interrupt, released for not busy/not in interrupt.
Level polling—Parallel Broadcast Polling: No part address
is sent, so all devices respond simultaneously. If a device
is busy/in interrupt, it will pull SDO low. If a device is not
busy/not in interrupt, then it will release the SDO line. If
any device is busy or in interrupt the SDO signal will be
low. If all devices are not busy/not in interrupt, the SDO
signal will be high. The master controller pulls CSBI high
to exit polling.
OPERATION
LTC6803-2/LTC6803-4
21
680324fa
OPERATION
Revision Code
The diagnostic register group contains a 2-bit revision
code. If software detection of device revision is neces-
sary, then contact the factory for details. Otherwise, the
code can be ignored. In all cases, however, the values of
all bits must be used when calculating the packet error
code (PEC) byte on data reads.
Bus Protocols
There are 6 different protocol formats, depicted in Table 3
through Table 8. Table 2 is the key for reading the protocol
diagrams.
Table 6. Address Poll Command
4 4 8 8 8
1000 Address PEC Command PEC Poll Data
Table 7. Address Read
4 4 8 8 8 8 … 8 8
1000 Address PEC Command PEC Data Byte Low … Data Byte High PEC
See Serial Command examples
Table 8. Address Write
4 4 8 8 8 8 … 8 8
1000 Address PEC Command PEC Data Byte Low … Data Byte High PEC
Table 4. Broadcast Read
8 8 8 … 8 8
Command PEC Data Byte Low … Data Byte High PEC
A bus collision will occur if multiple devices are on the same serial bus.
Table 5. Broadcast Write
8 8 8 … 8 8
Command PEC Data Byte Low … Data Byte High PEC
Table 2. Protocol Key
PEC Packet Error Code Master-to-Slave
N Number of Bits Slave-to-Master
... Continuation of Protocol Complete Byte of
Data
Table 3. Broadcast Poll Command
8 8
Command PEC Poll Data
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P40

LTC6803HG-2#PBF

Mfr. #:
Buy LTC6803HG-2#PBF
Manufacturer:
Analog Devices / Linear Technology
Description:
Battery Management Battery Stack Monitor, Addressable SPI
Lifecycle:
New from this manufacturer.
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