LTC6803-2/LTC6803-4
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To ensure pin compatibility with LTC6802-2, the LTC6803-2
is configured such that the bottom cell input (C0) is con-
nected internally to the negative supply voltage (V
–
). The
LTC6803-4 offers a unique pinout with an input for the
bottom cell (C0). This simple functional difference offers
the possibility for enhanced cell 1 measurement accuracy,
enhanced SPI noise tolerance and simplified wiring. More
information is provided in the Applications Information
section entitled Advantages of Kelvin Connection for C0.
V
+
(Pin 1): Positive Power Supply. Pin 1 can be tied to the
most positive potential in the battery stack or an isolated
power supply. V
+
must be greater than the most positive
potential in the battery stack under normal operation. With
an isolated power supply, LTC6803 can be turned off by
simply shutting down V
+
.
C12, C11, C10, C9, C8, C7, C6, C5, C4, C3, C2, C1
(Pins 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24): C1
through C12 are the inputs for monitoring battery cell
voltages. The negative terminal of the bottom cell should
be tied to the V
–
pin for the LTC6803-2, and the C0 pin for
the LTC6803-4. The next lowest potential is tied to C1 and
so forth. See the figures in the Applications Information
section for more details on connecting batteries to the
LTC6803-2 and LTC6803-4. The LTC6803 can monitor a
series connection of up to 12 cells. Each cell in a series
connection must have a common mode voltage that is
greater than or equal to the cells below it. 100mV negative
voltages are permitted.
C0 (Pin 26 on LTC6803-4): Negative Terminal of the Bot-
tom Battery Cell. C0 and V
–
form a Kelvin connection to
eliminate effect of voltage drop at the V
–
trace.
S12, S11, S10, S9, S8, S7, S6, S5, S4, S3, S2, S1 (Pins
3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25): S1 though
S12 pins are used to balance battery cells. If one cell in a
series becomes overcharged, an S output can be used to
discharge the cell. Each S output has an internal N-channel
MOSFET for discharging. See the Block Diagram. The NMOS
has a maximum on-resistance of 20Ω. An external resistor
PIN FUNCTIONS
should be connected in series with the NMOS to dissipate
heat outside of the LTC6803 package. When using the
internal MOSFETs to discharge cells, the die temperature
should be monitored. See Power Dissipation and Thermal
Shutdown in the Applications Information section. The S
pins also feature an internal pull-up PMOS. This allows the
S pins to be used to drive the gates of external MOSFETs
for higher discharge capability.
V
–
(Pin 26 on LTC6803-2/Pin 27 on LTC6803-4): Connect
V
–
to the most negative potential in the series of cells.
NC (Pin 27 on LTC6803-2/Pin 28 on LTC6803-4): This pin
is not used and is internally connected to V
–
through 10Ω.
It can be left unconnected or connected to V
–
on the PCB.
V
TEMP1
, V
TEMP2
(Pins 28, 29 on LTC6803-2/Pins 29, 30,
on LTC6803-4): Temperature Sensor Inputs. The ADC will
measure the voltage on V
TEMPn
with respect to V
–
and store
the result in the TMP register. The ADC measurements
are relative to the V
REF
pin voltage. Therefore a simple
thermistor and resistor combination connected to the
V
REF
pin can be used to monitor temperature. The V
TEMP
inputs can also be general purpose ADC inputs.
V
REF
(Pin 30 on LTC6803-2/Pin 31 on LTC6803-4): 3.065V
Voltage Reference Output. This pin should be bypassed
with a 1µF capacitor. The V
REF
pin can drive a 100k resis-
tive load connected to V
–
. Larger loads should be buffered
with an LT6003 op amp, or a similar device.
V
REG
(Pin 31 on LTC6803-2/Pin 32 on LTC6803-4): Linear
Voltage Regulator Output. This pin should be bypassed with
a 1µF capacitor. The V
REG
is capable of sourcing up to 4mA
to an external load. The V
REG
pin does not sink current.
TOS (Pin 32 on LTC6803-2/Pin 33 on LTC6803-4): Top
of Stack Input. The TOS pin can be tied to V
REG
or V
–
for
the LTC6803. The state of the TOS pin alters the operation
of the SDO pin in the toggle polling mode. See the Serial
Port description.
NC (Pin 33 on LTC6803-2): No Connection.
