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LTC6803HG-2#PBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P40
LTC6803-2/LTC6803-4
34
680324fa
APPLICATIONS INFORMATION
Figure 19. Using a V
TEMP
Input for Full-Stack Readings
the resistive loading on the cell group when the IC enters
standby mode (i.e., when WDTB goes low). An LT6004
micropower operational amplifier section is shown for
buffering the divider signal to preserve accuracy. This
circuit has the virtue that it can be converted about four
times more frequently than the entire battery array, thus
offering a higher sample rate option at the expense of
some precision/accuracy, reserving the high resolution
cell readings for calibration and balancing data.
Figure 20. Providing an Isolated High Speed Data Interface
–
+
1/2 LT6004
V
TEMP1
V
REG
WDTB
V
–
CELLGROUP
–
CELLGROUP
+
1
3
3
1
2
2N7002K
1µF
10nF
680324 F19
31.6k
2
4
8
499k
1M
PROVIDING HIGH SPEED ISOLATION OF THE SPI DATA
PORT
Isolation techniques that are capable of supporting the
1Mbps data rate of the LTC6803-2/LTC6803-4 require more
power on the isolated (battery) side than can be furnished
by the V
REG
output of the LTC6803-2/LTC6803-4. To keep
battery drain minimal, this means that a DC/DC function
must be implemented along with a suitable data isolation
circuit, such as shown in Figure 20. A quad (3 + 1) data
isolator Si8441AB-C-IS is used to provide non-galvanic
SPI signal connections between a host microprocessor
and an LTC6803-2/LTC6803-4. An inexpensive isolated DC/
DC converter provides powering of the isolator function
completely from the host 5V power supply. A quad three-
state buffer is used to allow SPI inputs at the LTC6803-2/
LTC6803-4 to rise to a logic high level when the isolator
circuitry powers down, assuring the lowest power con-
sumption in the standby condition. The pull-ups to V
REG
are selected to match the internal loading on V
REG
by ICs
operating with a current mode SPI interface, thus balanc-
ing the current in all cells during operation. The additional
pull-up on the SDO line (1k resistor and Schottky diode)
is to improve rise time, in lower data rate applications this
may not be needed.
V
DD1
GND1
A1
A2
A3
A4
EN1
GND1
V
DD2
GND2
B1
B2
B3
B4
EN2
GND2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Si8441AB-C-IS
QUAD ISOLATOR
1k
4.22k
V
REG
SDO
SCKI
CSB1
SCI
V
–
1µF1µF
BAT54S
CMDSH2-3
6
PE-68386
33nF
• •
4
1
3
12
13
1/4 74ABT126
11
2
1
1/4 74ABT126
3
5
4
1/4 74ABT126
6
8
10
1/4 74ABT126
74ABT126 SUPPLY SHARED WITH
ISOLATOR V
DD2
and GND2
9
4.22k
4.22k
4.22k
680324 F20
1µF
470pF
IN1
GND1
IN2
GND2
8
7
6
5
1
2
3
4
V
CC1
OUT1
V
CC2
OUT2
LTC1693-2
20.0k
100Ω
5V_HOST
100Ω
100Ω
100Ω
10.0k
SPI_CLOCK
SPI_CHIPSELECT
SPI_MASTEROUT
SPI_MASTERIN
GND_HOST
LTC6803-2/LTC6803-4
35
680324fa
APPLICATIONS INFORMATION
SUPPLY DECOUPLING IF BATTERY-STACK POWERED
As shown in Figure 21, the LTC6803-4 can have filtering
on both V
+
and V
–
, so differential bypassing to the cell
group potentials is recommended. The Zener suppresses
overvoltages from reaching the IC supply pins. A small
ferrite-bead inductor provides protection for the Zener, par-
ticularly from energetic ESD strikes. Since the LTC6803-2
cannot have a series resistance to V
–
, additional Schottky
diodes are needed to prevent ESD-induced reverse-supply
(substrate) currents to flow.
ADVANTAGES OF KELVIN CONNECTION ON C0
The V
–
trace resistance can cause an observable voltage
drop between the negative end of the bottom battery
cell and V
–
pin of LTC6803. This voltage drop will add to
the measurement error of the bottom cell voltage. The
LTC6803-4 separates C0 from V
–
, allowing Kelvin con-
nection on C0 as shown in Figure 22. Voltage drop on the
V
–
trace will not affect the bottom cell voltage measure-
ment. The Kelvin connection will also allow RC filtering
on V
–
as shown in Figure 21.
Figure 21. Supply Decoupling
Figure 22. Kelvin Connection on C0 Improving
Bottom Cell Voltage Measurement Accuracy
CELLGROUP
+
CELLGROUP
–
CMHZ5265B BAT46W
100Ω
100nF
V
+
V
–
BLM31PG330SN1L
LTC6803-2 Configuration
CELLGROUP
+
CELLGROUP
–
CMHZ5265B
100Ω
100Ω
100nF
680324 F21
V
+
V
–
BLM31PG330SN1L
LTC6803-4 Configuration
I
SUPPLY
68034 F20
BATTERY
STACK
R
+
+
+
+
C1
C0
V
–
LTC6803-4
LTC6803-2/LTC6803-4
36
680324fa
APPLICATIONS INFORMATION
HARDWARE SHUTDOWN
To completely shut down the LTC6803 a PMOS switch can
be connected to V
+
, or, V
+
can be driven from an isolated
power supply. Figure 23 shows an example of a switched
V
+
. The breakdown voltage of DZ4 is about 1.8V. If SHDN <
1.8V, no current will flow through the stacked MMBTA42s
and the 1M resistors. TP0610Ks will be completely shut
off. If SHDN > 2.5V, M7 will be turned on and then all
TP0610Ks will be turned on.
separation of traces at different potentials. The pinout
of the LTC6803 was chosen to facilitate this physical
separation. There is no more than 5.5V between any two
adjacent pins. The package body is used to separate the
highest voltage (e.g., 43.2V) from the lowest voltage (0V).
As an example, Figure 24 shows the DC voltage on each
pin with respect to V
–
when twelve 3.6V battery cells are
connected to the LTC6803.
Figure 24. Typical Pin Voltages for Twelve 3.6V Cells
Figure 23. Hardware Shutdown Circuit Reduces Total Supply
Current of LTC6803-4 to About 0µA
TP0610K
DZ3
15V
DZ4
1.8V
DZ1, DZ2, DZ3: MMSZ5245B
DZ4: MMSZ4678T1
ALL NPN: MMBTA42
ALL PN: RS07J
1M
50k
680324 F23
SHDN
V
+
V
–
C0
C12
LTC6803-4
IC #1
TP0610K
DZ2
15V
1M
D2
V
+
V
–
C0
C12
LTC6803-4
IC #2
TP0610K
DZ1
15V
1M
D1
V
+
V
–
C0
C12
LTC6803-4
IC #3
+
+
+
+
+
+
+
+
+
V
+
C12
S12
C11
S11
C10
S10
C9
S9
C8
S8
C7
S7
C6
S6
C5
S5
C4
S4
C3
S3
C2
CSBI
SDO
SDI
SCKI
A3
A2
A1
A0
GPIO2
GPIO1
WDTB
TOS
V
REG
V
REF
V
TEMP2
V
TEMP1
NC
V
–
C0
S1
C1
S2
43.2V
43.2V
43.2V
39.6V
39.6V
36V
36V
32.4V
32.4V
28.8V
28.8V
25.2V
25.2V
21.6
21.6
18V
18V
14.4V
14.4V
10.8
10.8
7.2
0V TO 5.5V
0V TO 5.5V
0V TO 5.5V
0V TO 5.5V
0V TO 5.5V
0V TO 5.5V
0V TO 5.5V
0V TO 5.5V
0V TO 5.5V
0V TO 5.5V
0V TO 5.5V
0V TO 5.5V
5V
3.1V
1.5V
1.5V
0V
0V
0V
3.6V
3.6V
7.2V
LTC6803-4
680324 F24
PCB LAYOUT CONSIDERATIONS
The V
REG
and V
REF
pins should be bypassed with a 1µF
capacitor for best performance. The LTC6803 is capable of
operation with as much as 55V between V
+
and V
–
. Care
should be taken on the PCB layout to maintain physical
ADVANTAGES OF DELTA-SIGMA ADCS
The LTC6803 employs a delta-sigma analog-to-digital
converter for voltage measurement. The architecture of
delta-sigma converters can vary considerably, but the
common characteristic is that the input is sampled many
times over the course of a conversion and then filtered or
averaged to produce the digital output code. In contrast,
a SAR converter takes a single snapshot of the input
voltage and then performs the conversion on this single
sample. For measurements in a noisy environment, a
delta-sigma converter provides distinct advantages over
a SAR converter.
While SAR converters can have high sample rates, the full-
power bandwidth of a SAR converter is often greater than
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P40

LTC6803HG-2#PBF

Mfr. #:
Buy LTC6803HG-2#PBF
Manufacturer:
Analog Devices / Linear Technology
Description:
Battery Management Battery Stack Monitor, Addressable SPI
Lifecycle:
New from this manufacturer.
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